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In this work, a new design approach in implementing low-energy, high-performance 64-bit adder using dynamic feedthrough logic (DFTL) is introduced and analyzed. Design issues of using DFTL in several logic depth are analyzed in order to achieve the best optimal balance between performance and power consumption. A ldquotiming windowrdquo technique is also proposed to reduce the amount of excessive...
In many DSP applications (image and voice processing, baseband symbol decoding in high quality communication channels) several dBs of SNR loss can be tolerated without noticeable impact on system level performance. For power optimization in such applications, voltage overscaling can be used to operate the arithmetic circuitry slower than the critical circuit path delay while incurring tolerable SNR...
In this work, we study how retiming can be used to reduce glitches in digit-serial recursive filters. It is a well known fact that glitches can make up a large portion of the dynamic power consumption in digital systems. Digit-serial recursive systems contain registers that can be retimed to reduce the amount of glitches. A second-order digit-serial LDI allpass filter has been implemented to verify...
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