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This paper focus on the implementation of configurable linear feedback shift register (CLFSR) in VHDL and evaluates its performance with respect to logic, speed and memory requirement in FPGA. Behavioral implementation of CLFSR in VHDL is configurable in terms of number of bits in the LFSR, the number of taps, positions of each tap in the shift register stage and seed value of LFSR. The target device...
HDB3 (High Density Bipolar)is an improved bipolar RZ code, based on the AMI. HDB3 has no DC component, less low-frequency components, the number of attached zeroes is no more than 3. All of the three advantages are beneficial to signal timing recovery. In this paper, by using modern EDA technology, and assistance of FPGA devices and the VHDL, we have designed and realized HDB3 encoder, which has overcame...
The new technological scenarios in digital systems demand the introduction of FPGA very early in digital design curricula. The approach that we present in the paper is based on a new tool that extends the features of Deeds, the design suite for digital circuits developed in our department. The FPGA extension allows students to compile a project generated with Deeds into an FPGA chip, reducing to a...
LFSR based PN Sequence Generator technique is used for various cryptography applications and for designing encoder, decoder in different communication channel. It is more important to test and verify by implementing on any hardware for getting better efficient result. As FPGAs is used to implement any logical function for faster prototype development, it is necessary to implement the existing design...
In this paper we have designed and implemented (15, k) a BCH Encoder on FPGA using VHDL for reliable data transfer in AWGN channel with multiple error correction control. The digital logic implementation of binary encoding of multiple error correcting BCH code (15, k) of length n=15 over GF (24) with irreducible primitive polynomial x4+x+1 is organised into shift register circuits. Using the cyclic...
One I2C protocol design method for reusability was proposed. In this method, design was divided into 3 levels: protocol level, signal level and interface level. Protocol level can be reused without any modification. Signal level can be reused by setting the number of be transferred byte according to specific operation. Interface level can be reused by changing the number of operation mode and the...
Today's machine automation systems are demanding for better throughput, faster response, built in safety features and high speed communication support, besides satisfying IEC61131-3 control specification. MEMS sensors & actuators along with increased control logic complexities are stretching limits of conventional Programmable Logic controllers (PLCs) generally used for industrial and high end...
This paper looks into prospects of pre-timed arterial traffic control systems for cities with limited infrastructures. The methodologies for designing a pre-timed arterial traffic controller system were researched. A prototype designed and implemented in field programmable gate arrays (FPGA) is presented. Dar es Salaam Roads have been used to provide data for the design and implementation whereby...
In this paper, a signal acquisition system for continuous-wave lidar is present in two ways. One is the hardware design, the other is the device design and application program design using FPGA with USB2.0 interface. The sampling rate of this system is up to 300Msps. The signal correlation and accumulation is processed by using FPGA with 512M RAM The experimental results show that it can be used in...
A VHDL design of a controller for the pre-amplifier and the ADC present on a Spartan-3E FPGA Starter Kit board has been carried out and tested using a function generator and an oscilloscope. The design is based on the Moore-type of finite state machine. The VHDL design is discussed and its results presented.
In this paper, a WiMedia UWB MAC layer is implemented in a FPGA development board. The MAC layer protocol is modeled by FSM technique and written in hardware description language. Combining the MAC layer design with other standard system peripherals, a FPGA-based UWB MAC reference design supporting UWB PHY layer specifications is synthesized. To verify the design, the FPGA platform works with a pair...
This paper describes the concept, architecture, development and demonstration of a 4-transmitter, real-time space-time encoder for multiple-input and multiple-output (MIMO) wireless systems. It is implemented on an FPGA chip in the Altera Stratix EP1S25 DSP Development Kit using VHDL. The system can be configured to use either space-time block coding (STBC) or space-time trellis coding (STTC). It...
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