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This paper investigates the use of novel hardware and techniques to increase the speed of simulation for large gas turbine engine models. In particular, the work shows the results of attempting to accelerate an engine system model using multiple processor cores and a FPGA co-processor. Strengths and weaknesses of the technologies are illustrated and an account of the lessons learnt for distributing...
Detailed architectural simulators suffer from a long development cycle and extremely long evaluation times. This longstanding problem is further exacerbated in the multi-core processor era. Existing solutions address the simulation problem by either sampling the simulated instruction stream or by mapping the simulation models on FPGAs; these approaches achieve substantial simulation speedups while...
An SoC framework is presented, comprising of a plug-and-play infrastructure where the system communication is abstracted from the processing elements. A software scheduler is used with a hardware modelling environment for latency analysis. Using the framework, an LTE uplink data channel (PUSCH) receiver design is shown to meet the stringent latency targets.
In this paper a common approach to design and testing of FPGA-based safety critical systems is given. The main idea for safety assurance and assessment of FPGA-based critical I&C systems lays in consideration of FPGA-chip as hardware and FPGA-project as software.
Stream architecture research is often hindered by slow software simulations. Simulators based on FPGA are much faster. However, larger scale stream architecture simulation needs more FPGA resource, which may result in more FPGA chips or larger capacity FPGA chip would be used. It not only increases the complexity of design, but also increases the cost of research. This paper proposed FPGA-based equivalent...
We present a practical, systematical method for the evaluation of the soft error rate (SER) of microelectronic devices. Existing methodologies, practices and tools are integrated in a common approach while highlighting the need for specific data or tools. The showcased method is particularly adapted for evaluating the SER of very complex microelectronic devices by engineers confronted to increasingly...
The rate compatible punctured convolutional code (RCPC code) is an important module in Multi-band Orthogonal Frequency Division Multiplexing Ultra Wide Band (MB-OFDM-UWB) indoor positioning system introduced in this paper as a kind of useful channel coding to offer more protection against all kinds of channel noise under indoor channel environments. In this paper, RCPC code for MB-OFDM-UWB indoor...
In this research, we analyze the power variations present in a router having varied number of ports, in a Networks- on-Chip. The work is divided into two sections, projecting the merits and shortcomings of a multi-port router from the aspect of power consumption. First, we evaluate the power variations present during the transfers between various port pairs in a multi-port router. The power gains...
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