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In this paper, improved architectures are proposed for implementation of S-Box and inverse S-Box needed in the Advanced encryption standard (AES) algorithm. These use combinational logic only for implementing SubByte (S-box) and InvSubByte (Inverse S-box). The composite field arithmetic used for implementing S-Box in lower-order Galois field (GF) investigated by several authors recently is used as...
The AES algorithm published in 2001 is now the most popular symmetric encryption algorithm. Several implementations have beed proposed but few of them considered the hardware cost and the throughput as a whole. This paper presents an AES core to be capable of both encryption and decryption with three different key lengths: 128-, 192-, and 256-bit. The overall hardware cost was optimized by a very...
This paper presents a high-throughput GCM VLSI architecture fully compliant to IEEE 802.1ae applications, which can be operated in all modes specified in the standard. Unlike previous works, with the modified parallel GHASH module, the design implements encryption efficiently without knowing the total number of data blocks in advance. Furthermore, a fully subpipelined version of loop-free key expansion...
Hardware signatures have been recently proposed as an efficient mechanism to detect conflicts amongst concurrently running transactions in transactional memory systems (e.g., bulk, LogTM-SE, and SigTM). Signatures use fixed hardware to represent an unbounded number of addresses, but may lead to false conflicts (detecting a conflict when none exists). Previous work recommends that signatures be implemented...
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