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Advanced Encryption Standard (AES) is one of the most common symmetric encryption algorithms. The hardware complexity in AES is dominated by AES substitution box (S-box) which is considered as one of the most complicated and costly part of the system because it is the only non-linear structure. The proposed work employs a combinational logic design of S-Box implemented in Virtex II FPGA chip. The...
In this paper, improved architectures are proposed for implementation of S-Box and inverse S-Box needed in the Advanced encryption standard (AES) algorithm. These use combinational logic only for implementing SubByte (S-box) and InvSubByte (Inverse S-box). The composite field arithmetic used for implementing S-Box in lower-order Galois field (GF) investigated by several authors recently is used as...
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