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The intension of this work is to design ASIC (Application Specific Integrated Circuit) for LFSRs (Linear feedback shift register) used in cryptography systems.(Stream ciphering). Presently FPGAs (Field Programmable Gate Array) and Processors are used for this purpose which have speed limitations. Since FPGAs have general structure and implementing LFSRs in FPGAs are unable to achieve the required...
Advance Encryption Standard (AES), has received significant interest over the past decade due to its performance and security level. In this paper, we propose a compact 8-bit AES crypto-processor for area constrained and low power applications where both encryption and decryption is needed. The cycle count of the design is the least among previously reported 8-bit AES architectures and the throughput...
This paper proposes a high-throughput cost-effective implementation of AES supporting encryption and decryption with 128-, 192-, and 256-bit cipher key. Optimum irreducible polynomial coefficients are selected to construct the composite field GF(((22)2)2) on standard and normal base in order to minimize the gate count in SubBytes/InvSubBytes transformation. In addition, MixCoulmn/InvMixColumn transformations...
In this paper, we present a new block cipher, referred as PUFFIN2, that is designed to be used with applications requiring very low circuit area. PUFFIN2 is designed to be implemented exclusively with CMOS technologies and in a serialized architecture, so that the maximum reuse of hardware components is achieved resulting in a very compact implementation. PUFFIN2 has a block size of 64 bits and a...
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