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Self-healing ability is recognized as an important contributor in building embedded systems that require a high level of robustness and reliability, especially if they operate in an unpredictable environment or hard to reach places where any repair is difficult. This paper presents a systematical comparison of the state of the art biologically inspired approaches to self-healing in embedded systems...
Reliability evaluation is a critical task in computing systems. From one side, the results must be accurate enough not to under-or over-estimate the overall system reliability (thus either resulting in a non-reliable system, or a system for which too expensive solutions have been adopted). On the other side, the time required for the analysis should be kept at the minimum. This paper presents some...
We consider the problem of evaluating the performance of a 5G network based on reusable components, called Reusable Functional Blocks (RFBs), proposed by the Horizon 2020 SUPERFLUIDITY project. RFBs allow a high level of flexibility, agility, portability and high performance. After formally modelling the RFB entities and the network physical nodes, we optimally formulate the problem of maximizing...
Cache timing attacks have been known for a long time, however since the rise of cloud computing and shared hardware resources, such attacks found new potentially devastating applications. One prominent example is S$A (presented by Irazoqui et al at S&P 2015) which is a cache timing attack against AES or similar algorithms in virtualized environments. This paper applies variants of this cache timing...
This paper presents a novel bit-serial fine-grain pipelined reconfigurable VLSI architecture based on multiplexer logic to achieve high utilization of hardware resources and high throughput. A basic cell is constructed by a logic block composed of a 2-data-input multiplexer and a switch box for data transfer between adjacent logic blocks by 8-near neighborhood mesh network. A multiplexer merged with...
This paper discusses the development and evaluation of a Cellular Neural Network (CeNN) friendly deep learning network for solving the MNIST digit recognition problem. Prior work has shown that CeNNs leveraging emerging technologies such as tunnel transistors can improve energy or EDP of CeNNs, while simultaneously offering richer/more complex functionality. Important questions to address are what...
In the information security field, varions algorithms are applied to provide users with a variety of security services. Although many of the algorithms are implemented in software, there is a rapidly growing demand for hardware implementations. The BlaMka algorithm is a cryptographic sponge algorithm, used in password hashing schemes (PHS) such as Lyra2 and Argon2, which are algorithms that generate...
This paper introduces a scalable hardware design to accelerate the maze algorithm for VLSI routing on Cellular automata (CA). The time-complexities of wave-propagation and back-tracing on CA are both O(n) while constant time for label clearing. Innately high parallelism of CA largely reduces the runtime in wave propagation and label clearing. The RTL implementation for this design has been developed...
Complex computing platforms involving pipelined processors, memory hierarchies, multi-core and many-core architectures are very common nowadays. These approaches require a deep understanding of the underlying hardware and the corresponding programing model to be able to decide which alternative is more suitable, i.e. obtain the best performance at the minimum cost, for a given application. Hence,...
Advanced process technology allows high memory density. However, the memory cell shrinkage introduces more memory defects and this causes a memory yield problem. To overcome the issue, memory ECC has become a critical solution. This paper proposes a hardware architecture to support memory ECC utilizing memory spares. Overheads imposed by the proposed architecture are analyzed and compared against...
Physically Unclonable Function (PUF) is cost effective and reliable security primitives widely used in authentication and in-place secret key generation. With growing research in the area of non-CMOS technologies for memories and circuits, it is important to understand their implications on the design of security primitives. Resistive Random Accessible Memory (RRAM) offers easy integration with CMOS...
The real-time monitoring of status parameters, such as cell voltage and state of charge (SOC), is an important guarantee of the safety operation of the battery energy storage system (BESS). And the two-level architecture of hardware system which includes several battery management units (BMU) and the central management unit (CMU) is designed with the communication protocol and data conversion algorithm...
This paper designed an audio driver based on ASoC framework. All the work was based on Linux operator system which is composed of Exynos4412 microprocessor and wm8960 codec audio chips. In the system, the audio driver can drive multiple codec cards, the I2C bus is used to transmit the control information to the audio chip, and the I2S bus is used to transmit the audio data. ASoC audio driver architecture...
Feature extraction, which is one of the basic tasks for pattern recognition, has often high computational cost and large memory usage. In this work, we propose a pixel-based pipeline hardware architecture for Haar-like feature extraction, implemented in 0.18 μm CMOS technology with 1.76 mm2 core area. Pixel-input speed relies on the working frequency of the image sensor so that features are extracted...
This paper presents the implementation of Rijndael S-Box using combinational logic for the SubByte transformation in the Advanced Encryption Standard algorithm for ASIC. The main focus of this project is on achieving reduction in area occupancy and power consumption for the S-box module. We have realized an optimized implementation of the S-box in the Verilog HDL, and have subsequently synthesized...
This paper presents the design and implementation of a 64-bit VLIW microprocessor. It discusses the concept, traits, principle and structure of this 64-bit VLIW microprocessor to facilitate its design. This paper first discusses the architectural specifications of the microprocessor and the 16 kinds of operational functions it facilitates. It then examines the implementation of the whole VLIW microprocessor...
Reliability evaluation is a high costly process that is mainly carried out through fault injection or by means of analytical techniques. While the analytical techniques are fast but inaccurate, the fault injection is more accurate but extremely time consuming. This paper presents an hybrid approach combining analytical and fault injection techniques in order to evaluate the reliability of a computing...
Physically Unclonable Functions (PUF) are the cost effective and reliable security primitives widely used in authentication and in-place secret key generation applications. With growing research in the area of non-CMOS technologies for memories and circuits, it's important to understand their implications on the design of security primitives. Resistive Random Accessible Memory (RRAM) offers easy integration...
This work presents the development and FPGA implementation of a QR Decomposition Processor capable of solving the Recursive Least Squares (RLS) algorithm.
The various application scenarios of a battery system lead to versatile, often conflicting requirements for hardware, software and mechanical design. The intended use of a lithium-ion battery system in mobile and stationary applications determines a lot of restrictions such as design space and ambient conditions. Additional hardware and software requirements are dictated by engineering constraints...
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