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This paper jointly considers the mechanisms of rate control and the rate-distortion optimization (RDO) for the H.264/AVC hardware encoder. The proposed architecture performs intra prediction and inter prediction with our rate control mechanism in the first two stages. In addition, a low complexity macroblock (MB)-level mean absolute difference (MAD) prediction algorithm which considers both the motion...
As the video resolution increases, high computational complexity of the fractional motion estimation (FME) introduces difficulty to meet real-time constraints in a video coding. In this paper, we proposed a single-pass FME algorithm and its architecture with low hardware cost and negligible loss of the image quality. The proposed algorithm directly searches only surroundings of both the predicted...
Region-of-interest (ROI) can be applied in H.264 video encoder to enhance subjective quality and reduce computation complexity. For the aiming application of low cost hardware real-time encoder in videophone with faces as ROI, this paper proposes a face detection algorithm to detect each macroblock (MB) as one part of a face or not. This face detection algorithm has a unique estimation-and-verification...
Intra coding in H.264/AVC has significantly enhanced the video compression efficiency. However, computation complexity increases due to the rate-distortion (RD) based mode decision. This paper proposes a new fast mode decision algorithm in H.264/AVC intra prediction and its VLSI architecture. A new edge-detection pattern is proposed and both edge-detection technique and spatial mode prediction technique...
The H.264/AVC standard allows for a high compression efficiency at the cost of computational complexity. To achieve as high as possible efficiency, the proposed architecture supports the mode selection based on the rate-distortion optimization. In particular, the dataflow assumes throughput of 32 samples/coefficient per clock cycle, on average, allowing a lot of compression options to be checked....
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