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This paper presents the development of a 64-channel Field Programmable Gate Array (FPGA) based digital beamformer for real-time ultrasonic elastography imaging. The hardware architecture is controlled by Altera Cyclone III FPGA ICs (EP3C16Q240, Altera Corporation) and allows flexibility for programmable aperture windowing, multiple transmit focusing phase adjustment, amplitude apodization, and dynamic...
We present a novel algorithm for reconstructing interferograms acquired in optical frequency domain imaging (OFDI). The algorithm was developed specifically for processing in field programmable gate arrays (FPGAs) and featured the use of a finite-impulse-response (FIR) filter implementation of B-spline interpolation for efficiently re-sampling k-space. When implemented in FPGAs, the algorithm allowed...
In this paper we propose hardware architecture of the embedded software modem platform. The hardware platform consist of a single S3C2410 ARM which its operation speed is 200 MHz, three TMS320C6416T DSPs which has a 1GHz clock, a single Stratix II EP2S60F672C5 FPGA which has 900 K gates and two two-channel ADCs and DACs which can support up to 125 MHz sampling rate. The embedded Linux 2.4 is ported...
Eight independent multi-rate signal interpolators, with real-time change of rate capability, were implemented on a field programmable gate array. The interpolator main building blocks are a cascaded integrator-comb (CIC) filter and the respective compensation filter. The latter performs a fixed rate change of 4 and was implemented as a 129 taps finite impulse response (FIR) filter. The FIR filter...
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