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Continuous reduction in the minimum feature size of semiconductor devices and the supply voltages in advanced VLSI logic circuits has made those circuits more susceptible to soft errors. Hence, several fault tolerance techniques have been proposed in the literature to protect combinational circuits against single event transients (SETs). These fault tolerance techniques are based mainly on hardware...
Extra circuitry for concurrent error detection (CED) schemes is becoming an essential feature as IC technologies continue to scale. Soft errors have emerged as an important challenge in the nanoscale design and several works are dedicated to quantify the CED effective enhancement in systems dependability, but none of them makes a comprehensive description of the output events that can occur in such...
Sets of Pairs of Functions to be Distinguished (SPFD) is a functional flexibility representation method that was recently introduced in the logic synthesis domain, and promises superiority in exploring the flexibility offered by a design over all previous representation methods. In this work, we illustrate how the SPFD of a particular wire reveals information regarding the number of potential transient...
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