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Active magnetic bearings (AMBs) represent an innovative contact free suspension technology with many advantages such as online adaptability of bearing stiffness and damping which makes AMBs especially suited for high speed rotor applications. Disadvantageous is the rather high system complexity which leads to a reduced overall reliability. To enhance AMB's reliability a new AMB concept has been developed...
In this paper, we present a new design of TAS-MRAM, which is dedicated for the embedded applications. The Thermally Assisted Switching (TAS) approach allows the low power memory programming and Pre-Charge Sense Amplifiers (PCSA) enable the reliable, high speed and low power sensing. By using a TAS-MTJ spice model integrating the precise experimental parameters and CMOS 130nm technology, simulations...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
As semiconductor technology moves closer to the ultimate physical limits for scaling of devices that utilize electrons as information bearing particles, many new opportunities for research in the physical sciences are emerging. If we look beyond the limits of scaling electron devices, many more challenging research opportunities exist in the areas of physics of information carriers and physics of...
Multi-core SoC created great opportunities to increase overall system performance while keeping the power in check but also created many design challenges that designers must now overcome. The challenge of doubling performance every two years used to drive superscalar design with more functional units running concurrently or deeper pipeline racing for highest frequency at the cost of higher power...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
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