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As process technology continues to shrink, interconnect current densities continue to increase, making it ever more difficult to meet chip reliability targets. For microprocessors in the latest 32nm processes, interconnect wear-out via electromigration is as critical a design parameter, if not more so, as timing, power, and area, and must be planned for from the outset. This paper presents a true...
As semiconductor technology moves closer to the ultimate physical limits for scaling of devices that utilize electrons as information bearing particles, many new opportunities for research in the physical sciences are emerging. If we look beyond the limits of scaling electron devices, many more challenging research opportunities exist in the areas of physics of information carriers and physics of...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
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