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Saving power consumption is the most important aspect of nanoscale ASIC and system-on-chips (SOCs). At the same time, due to the low supply voltage and reduced node capacitance, nanoscale integrated circuits are highly susceptible to energetic particle-induced transient data upsets (SEUs). In this paper, we propose a high-speed SEU hardened flip-flop. The flip-flop consists of a unique soft error...
Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random logic is in the order of the number of SRAM cells on chips only a few years ago. Often latches are clock gated and have to retain their states during longer periods. Moreover, miniaturization has led to elevated susceptibility...
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