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The paper presents an innovative concept of the new area measuring algorithm and new area decision algorithm for power lines' distance protection. These algorithms improve the operating conditions of the distance protection. The primary purpose of the new measuring algorithm is correct the short-circuit impedance calculation. The purpose of the new decision algorithm is correct identify of the line...
The time-triggered principle establishes and maintains a system-wide synchronized time-base by the local clocks of the device. The proposed concept of Time-Triggered Ethernet (TTE) guarantees the determinacy of time-critical message for avionics and safety-critical systems. This paper presents an algorithm based on path-hop of tasks to generate a rational scheduling timetable to ensure is free of...
Job scheduling is a important purpose of the running process. Laptop assets are scheduled earlier than use. By means of switching the CPU among techniques, the operating procedure can make the computer more productive. All fundamental CPU scheduling algorithms targets at maximizing the CPU utilization, throughput, and minimizing waiting time, turnaround time and context switch. To beef up the efficiency...
Nowadays, virtualization is an important technique that offers illimited resources to network users. It allows users to share switch's resources in time and space. Sharing in time is done by scheduling algorithms determining at which moment each input queue is matched with an output queue. Regarding sharing in space, it takes place in the queues which are split into multiple virtual queues. Being...
The ever increasing demand for more bandwidth at core routers has been a challenge for switch design. To address the challenge, parallel packet switches (PPSs) combine multiple parallel switching fabrics and provide huge aggregate bandwidth. However, most existing PPSs handle only fixed length packets, also called cells, mainly because traditional switching fabrics can process only cells. Since packets...
FPGA dynamic partial reconfiguration (DPR) tend to be adopted for its flexibility and fewer resource consumption increasingly in hardware implementation, especially in communication devices. A crossbar scheduling algorithm is used to schedule the crossbar, or decide the order in which cells will be served. The is lip and FIRM are two classic crossbar scheduling algorithms, but they do not support...
Switch is the kernel of Avionics Full Duplex Switched Ethernet (AFDX) network, and its scheduling algorithm affects the switch's performance directly. Employing the Earliest Deadline First (EDF) scheduling method in the switch of AFDX network can overcome the disadvantages of Quality of Service (QoS) for emergent messages. EDF scheduling algorithm assigns a priority level for each arriving message,...
Virtual prototypes are widely employed in today's development of embedded hardware and software. To model and simulate the VPs, SystemC has been adopted as a standard language tool. With SystemC, hardware modules and software codes can be modeled as processes. To model concurrency, one process can be suspended and then the SystemC scheduler selects the next process to resume. This is also known as...
Automated three-dimensional warehouse plays an increasingly important role in the production and storage of enterprise. It has become one of the key factors that restrict the development of enterprises. Based on the analysis of the actual demand of the company in Nanjing, the writer put forward a mechanism that replaces the stacker runtime with the number of the cargo columns. And integrated the principle...
In this paper, we propose a 3-stage framed packet switch using an internal speedup of 2 to avoid any control loop between any two stages of the switch. The switch segments the arriving variable-length packets at each input port into fixed-size cells and assembles the cells into frames. Then the frames are switched across the shared buffers to their destined output ports, and the cells are reassembled...
The method of network coding has been proven a promising solution to fanin conflict problems (traffic flows conflicting at input ports) in multicast switches in previous work. However, this approach is inefficient when applied to frame-based switches because of over-splitting with conventional algorithms. These algorithms do not support the benefits of network coding to be fully realized when ignoring...
This paper argues the need for "smart edge" devices to enhance the performance, functionality, and security of data center networks. Three examples, drawn primarily from the prior networking literature, are used to illustrate this point. The first example is the TCP in-cast problem, wherein highly concurrent TCP flows traverse a limited-buffer LAN switch, degrading system throughput. The...
In this paper, we present an embedded platform for real-time emulation of nonlinear electrical circuits in an embedded processor. Electrical systems, if complex, are better implemented if split into number of tasks. These tasks will have different priorities and timing deadlines and hence must be managed by an Operating System. We present and evaluate an iteration time based adaptive time step scheduling...
This paper introduces the concept of switched FlexRay networks and proposes two algorithms to schedule data communication for this new type of network. Switched FlexRay networks use an intelligent star coupler, called a switch, to temporarily decouple network branches, thereby increasing the effective network bandwidth. Although scheduling for basic FlexRay networks is not new, prior work in this...
Input-queued (IQ) switches are one of the reference architectures for the design of high-speed packet switches. Classical results in this field refer to the scenario in which the whole switch transfers the packets in a synchronous fashion, in phase with a sequence of fixed-size timeslots, selected to transport a minimum-size packet. However, for switches with large number of ports and high bandwidth,...
Most of today's high capacity switches and Internet routers do not provide performance guarantees. This is attributed to their underlaying interconnection topology (i.e. the crossbar) and/or to their impractically complex scheduling algorithms. This paper derives a study for a Partially Buffered Crossbar (PBC) switch to practically provide throughput and fairness guarantees. We show how a PBC switch...
We consider an N×N input-queued switch based on a crossbar switching fabric implemented on a single chip. The thermal power produced by the crossbar chip grows as N R3, where R is the maximum bit rate. Power dissipation is becoming more and more challenging, limiting the crossbar scalability for high performance switches. We propose to exploit Dynamic Voltage and Frequency Scaling (DVFS) techniques,...
A parallel packet switch (PPS) provides huge aggregate bandwidth by combining the capacities of multiple switching fabrics. Most existing PPSs use output queued switches as the switching fabrics, which require speedup and result in high implementation cost. In this paper, we present a buffered crossbar based parallel packet switch (BCB- PPS), whose switching fabrics need no speedup. We propose the...
Delay bounds of data transmissions and system buffer bounds are important parameters of quality of service (QoS) in networked control systems (NCS). They are particularly important for the analysis and design. Generally, the characteristic of round-trip time (RTT) of the switched Ethernet used in NCS can leads to increased burst and buffer loss. And the bandwidth allocated to a switch is highly affected...
We describe the methodology; the design and the implementation of scheduler block of interconnect. The scheduler block is implemented in Verilog using SYNOPSYS tool's DVE and Design_vision. The interconnect is capable of handling 72 bit packets and a total of 32 packets at a time. There are total 8 devices and we have to establish the communication between them. Each device consists of an input block...
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