The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Logical elements with Single-Event Transients Compensation were simulated on the base of the bulk 28-nm CMOS design rule. The result of an impact of a single nuclear particle on MOS logical gate is a noise pulse, being a single-event transient. The combinational logic of error decoder can prevent all noise pulse propagating through NAND and NOR gates for the output state null “0” of bits error decoder...
The quaternary logic system has evolved from and closely related to binary logic system. The logic is capable of handling both quaternary and coupled binary inputs, where binary operands are coupled in pairs to form quaternary entities. A set of operators capable of handling both coupled-binary and ordinary inputs are used. To demonstrate the functionality of this novel logic scheme, some useful logic...
In this paper, the architecture of an SOA-based N-bit decoder, with minimum number of SOAs using Cross-Gain Modulation (XGM), is described. A 2-bit decoder is integrated under Multi-Project Wafer (MPW) photonic foundries in indium phosphide (InP) technology. Its output signals are analysed off chip and its performance is evaluated at 10 Gbps with RZ amplitude-modulated signals.
This paper presents an efficient min-sum-based decoder for high-rate low-density parity-check (LDPC) codes, where the first minimum and second minimum values are stored in registers. In order to meet a strict cost requirement imposed by NAND flash applications, we provide different upper limits for the first and second minimum values. Furthermore, we use non-uniform quantization for the second minimum...
The main aim of VLSI designers being low power design, this paper presents a CMOS-based new design approach for a low power adiabatic 4∶2 Priority Encoder and a 2∶4 Decoder. The proposed designs are compared with the standard adiabatic logic styles- PFAL, ECRL and 2n2n2p, revealing lesser power consumption. The simulation is carried out in NI-Multisim software at 0.5 µm CMOS technology for frequency...
What decoder is, everyone knows. The paper presents a method of n-to-2n-lines decoders design in easy way. Based on a few building blocks only, especially prepared, and appropriate procedure of their placement, a decoder of any size can be build. Layouts of all needed fundamental blocks were designed in CMOS technology, as standard library Moreover, some important parameters, such area, power dissipation...
This paper demonstrates the reversible logic synthesis for the n-to-2n decoder, where n is the number of data bits. The circuits are designed using only reversible fault tolerant Fredkin and Feynman double gates. Thus, the entire scheme inherently becomes fault tolerant. Algorithm for designing the generalized decoder has been presented. In addition, several lower bounds on the number of constant...
A Memristor is a nonlinear resistor with memory, and is considered as the fourth type of basic circuit element except resistor, capacitor and inductor. With special circuitry characteristics, memristor can be used for both information storage and logic operations. In traditional Von Neumann computer architecture, address decoder is an important component connecting processor and memory. This paper...
Reversible computation differs from traditional computation in that it preserves information while manipulating it. This new design paradigm has very attractive thermodynamic consequences and holds many applications in current and emerging technologies. Modern computers can reduce power consumption by taking advantage of reversibility, and quantum computers operate reversibly. Researchers have already...
Reversible logic is an emerging nanotechnology widely being considered as the potential logic design and implementation of nanotechnology and quantum computing with the main goal of reducing physical entropy gain. Recent advances in reversible logic allow for new avenues in the implementation of reversible combinational circuits. Part of this advancement is the design and implementation of a finite...
A new design approach of the LDPC decoder based on FPGA Impulse C Programming is proposed. The latest technique of Impulse C programming is used to implement hardware circuit, which is more efficient than the traditional HDL method. The decoder for a family of (3,6) LDPC Codes with 0.5 code rate and the block size of 2500 bits is implemented on Xilinx Virtex2 XC2V2000. When the maximum iteration time...
A decoder is a hardware module that expands an x-bit input into an n-bit output, where x ?? n. It can be viewed as producing a set P of subsets of an n-element set Zn. If this set P can be altered by the user, the decoder is said to be configurable. In this paper we propose a class of configurable decoders (called ??mapping-unit?? based decoders or simply MU-decoders) that facilitate efficient selection...
Our paper presents the prototyping of a BCH (Bose, Chaudhuri, and Hocquenghem) encoder and decoder using a Field Programmable Gate Array (FPGA) reconfigurable chip. These types of codes are used in communications networks to detect and correct errors. Typically, the algorithms that implement these codes are sequentially type. Our solution is a combination of a parallel and a sequential implementation...
A new technique for controlling the bit-rate of H.264 encoded sequences is presented. The technique achieves bit-rate control by dropping frames directly in the compressed domain. The dropped frames are carefully selected so as to either eliminate or cause non perceptible drift errors in the decoder. The technique suits well for H.264 encoded sequences such as movies and tv news, which are transmitted...
In this paper, we propose the design method and the structure of a decoder with shortened cyclic code for radio data systems (RDS). Without microprocessor the logic gates are used to implement the hardware of the decoder, moreover, the decoder not only can decode the received message of RDS, but also has the functions of synchronization, error detection and error correction. The proposed decoder includes...
A completely new scheme for quaternary logic is proposed. Instead of conventional fuzzy logic or Galois Field theory, the logic system is based on the extension of Boolean algebra. The logic is capable of handling both quaternary and coupled-binary inputs, where binary operands are coupled in pairs to form quaternary entities. All necessary operators are defined and several theorems and properties...
A new scheme for quaternary logic is proposed. The logic system is based on the extension of Boolean algebra, instead of conventional Fuzzy logic or Galois Field theory. This logic mainly focuses on the capability of handling coupled-binary input, where binary operands are coupled in pairs to form multivalued entities. Several operators are defined and a fully operational algebra is developed. To...
In this paper the design and simulation of a single-electron 2-4 decoder based on NAND gates is presented. The simulation was made using a Monte-Carlo based tool. The results confirmed that the circuit was behaving as a 2-4 decoder. The stability plot and the free energy history diagrams offer detailed analysis of the circuit. The results were compared to similar circuits reported in the literature...
We present the design of quaternary quantum version of reversible circuits such as Toffoli gate, modified Fredkin gate, mux, demux, encoder-decoder using linear ion realizable quaternary Muthukrishnan-Stroud gates. Our realization of quaternary Toffoli gate is more efficient than the previous realization and other quaternary circuits are realized for the time in literature.
We propose a distributed source coding system for data collected by sensor networks. It uses a feedback channel between the sensors and the gateway node (i.e., the joint decoder) but, unlike previous systems, the encoding process is driven by the decoder. Compression is performed using distributed arithmetic coding, which is extended to adaptively estimate the source probabilities. Specifically, the...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.