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We have proposed a new security platform: physical unclonable function (PUF) matching using programmable delay lines (PDL). Our platform inherits good security properties of standard PUFs, such as low energy, low delay, and unclonability. However, standard PUF-based security protocols induce high computational resources of at least one involved party. To resolve this issue, we take advantage of PDL...
This paper presents the fast carry chain adder using Instantiation design entry which facilitates the direct design of the components through exact placement of the individual blocks in FPGA. The basic n-bit adder is divided into n/3 number of ripple carry adders with carry inputs generated from separate carry generator. The carry generator is designed on LUT by using all the six inputs with 100%...
Floating-point arithmetic is ever-present in computer systems. All most all computer languages has supports a floating-point number types. Most of the computer compilers called upon floating-point algorithms from time to time for execution of the floating-point arithmetic operations and every operating system must be react virtually for floating-point exceptions like underflow and overflow. The double-precision...
Redundant number systems provide carry-propagation free arithmetic, so that faster arithmetic circuits can be designed. In this work, an alternative redundant arithmetic based fused multiply-accumulate (MAC) unit is designed especially suitable for 6-input look-up-table (LUT) based FPGAs. By employing only (6, 3) counters in the partial product reduction and accumulate operations, least amount of...
Arbitrary binary waveforms are needed for chip testing and for operating complexly-controlled devices. Such signals are required to be glitch-free and might have to be as fast as the fastest clock available, thus with transitions coinciding with both positive and negative clock edges, which prevents the use of conventional (by means of D-type flip-flops) deglitching of the generated signals. This...
Cryptography is a method that has been developed to ensure security of messages and transfer of data. Advanced Encryption Standard (AES) is the first choice for many critical applications. The AES is a Federal Information Processing Standard (FIPS) which is cryptographic algorithm used to protect electronic data. Implementations of the Advanced Encryption Standard (AES) have rapidly grown in various...
In classical FPGA, LUTs and DFFs are pre-packed into BLEs and then BLEs are grouped into logic blocks. We propose a novel logic block architecture with fast combinational paths between LUTs, called pattern-based logic blocks. A new clustering algorithm is developed to release the potential of pattern-based logic blocks. Experimental results show that the novel architecture and the associated clustering...
While asynchronous techniques are of increasing interest in low-power design, designers cannot simply transfer current synchronous techniques to that domain. In particular, commercial FPGA systems and their accompanying EDA tools are not well suited to asynchronous logic design. In this paper we describe and analyze five alternative description methods that allow Null Convention Logic (NCL) based...
In today's semiconductor industry we see a move towards smaller technology feature sizes. These smaller feature sizes pose a problem due to mismatch between identical cells on a single die known as local variation. In this paper a library tuning method is proposed which makes a smart selection of cells in a standard cell library to reduce the design's sensitivity to local variability. This results...
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