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A design of a low skew clock distribution network is presented based on the TSMC 0.18 ??m CMOS technology. This work first investigated various aspects in designing a clock distribution network. After that, the design methodology for the chosen H-Tree clock network topology is presented. A series of design performance analyses such as clock delay, skew, rise and fall time, supply voltage and temperature...
In this paper, we propose an X-architecture routing algorithm for a clock network. With the definition of 16-pattern X-routing for a pair of points, our algorithm applies these patterns to simplify the selection of merging segments whereas using the DME approach and constructs an X-clock tree with zero skew. An X-flip is employed to shorten the wire length of each pair of points as possible for minimal...
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