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Dataflow modeling techniques facilitate many aspects of design exploration and optimization for signal processing systems, such as efficient scheduling, memory management, and task synchronization. The lightweight dataflow (LWDF) programming methodology provides an abstract programming model that supports dataflow-based design and implementation of signal processing hardware and software components...
Electronic System Level (ESL) design flow tries to handle the complexity of today's System-on-Chip design and verification. Due to this complexity, design and verification methodologies start from an abstraction level higher than Register Transfer Level (RTL). In ESL, verification becomes a major bottleneck in the design flow, and finding a good verification methodology at this abstraction level is...
Custom hardware accelerators are widely used to improve the performance of software applications in terms of execution times and to reduce energy consumption. However the realization of an hardware accelerator and its integration in the final system is a difficult and error prone task. For this reason, both Industry and Academy are continuously developing Computer Aided Design (CAD) tools to assist...
Chisel is a hardware construction language that supports a simplistic level of transactional programming via its Decoupled I/O primitives. In this paper we describe extensions that layer popular design paradigms on the Chisel substrate. We include RTL, SAFL-style functional hardware description, Handel-C message passing and Bluespec rules. We then briefly discuss interworking between these design...
In recent years there has been a great interest in High Level Synthesis (HLS) CAD tools to raise the level of design abstraction, reduce design time, rapidly explore the design space and fully exploit the multi-million gate heterogeneous hardware platforms provided by dramatic improvements in integrated circuits. Open Computing Language (OpenCL) is a well-known standard for heterogeneous computing...
Computer architects are increasingly interested in evaluating their ideas at the register-transfer level (RTL) to gain more precise insights on the key characteristics (frequency, area, power) of a micro/architectural design proposal. However, the RTL synthesis process is notoriously tedious, slow, and errorprone and is often outside the area of expertise of a typical computer architect, as it requires...
Balsa provides a rapid development flow, where asynchronous circuits are created from high-level specifications, but the syntax-driven translation used by the Balsa compiler often results in performance overhead. To reduce this performance penalty, various control resynthesis and peephole optimization techniques are used, in this paper, STG-based resynthesis is considered. For this, we have translated...
This paper conceptualizes and comments an Hardware-In-the-Loop-based methodology for the design and test of wireless links based on Impulse-Radio UWB. The paper analyses standard HDL simulation EDA tools for interfacing compatibility with the physical peripherals in a generic HIL configuration to define a general Hardware-In-the-Design methodology, i.e. the HIL validation in the first steps of a standard...
A flexible and efficient fixed to floating point conversion tool is presented for digital signal processing and communication systems. Fixed point numbers are heavily used in digital systems because they require less hardware, verification time and design effort compared to floating point number systems. However, floating point numbers offer better precision. Some digital designs may use a hybrid...
Field Programmable Gate Arrays (FPGAs) are becoming increasingly popular for use in high-integrity safety related and safety critical systems. FPGAs offer a number of potential benefits over traditional microprocessor based software systems, such as predictable timing performance, the ability to perform highly parallel calculations, predictable emulation of obsolete components, and (in the case of...
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