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We have investigated the impact of plasma-induced charging damage on the hot carrier reliability of n- and p-MOSFET's, including the examination of different stress bias regimes and the statistical distributions of hot carrier failure times. We found that when electron trapping determines hot carrier failure-as in p-MOSFETs stressed under the peak gate current condition-the median time-to-fail was...
The hot-carrier-injected oxide region is systematically investigated for fully depleted surface-channel (SC) nMOS and SC- and buried-channel pMOSFETs fabricated on an ultra-thin (50 nm)-film SIMOX wafer. NMOSFET degradation is shown to be caused mainly by hot-carriers injected into the drain side of the front oxide and pMOSFET degradation by hot-electrons injected into the drain side of both the back...
The purpose of this paper is to study nMOS hot carrier reliability dependence on gate oxide thickness in 0.35 /spl mu/m devices. It is found that the gate oxide thickness effect in 0.35 /spl mu/m NMOS is primarily due to channel inversion charge difference and not due to smaller mobility degradation in thinner oxide as previously reported for 0.8 /spl mu/m NMOS.<<ETX>>
A simple method is proposed to quantitatively evaluate hot carrier reliability of a plasma-stressed PMOSFET using its characteristic degradation measured before forming gas annealing. This method is used to deduce a plasma-stress equivalent charging current. This plasma current increases with a decrease in gate oxide thickness. The hot carrier reliability of thinner oxides, however, is less influenced...
This paper investigates the physics of voltage and temperature accelerated breakdown testing of silicon dioxide within the framework of an anode hole injection model which can predict low voltage (3.3 V and below) breakdown lifetime. The field acceleration rate is shown to be independent of temperature, while the reduction of oxide breakdown lifetime at increased temperature is due to the oxide's...
ESD protection capability of SOI CMOS output buffers has been studied with human body model (HBM) stresses of both positive and negative polarity. Experimental results show that the ESD discharge current is absorbed by the NMOSFET alone. Unlike bulk technologies where the bi-directional ESD failure voltages are limited by positive polarity stresses, SOI circuits display a more serious reliability...
Analyses have been performed on floating-gate avalanche-injection MOS transistor (FAMOS) devices which have been subjected to write/erase cycling, resulting in hole injection into the tunnel dielectric. Theoretical and experimental analysis of these devices have shown that the bits which exhibit fast erase due to these trapped holes are highly modulated by the field across the tunnel dielectric. Two...
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