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This paper presents the design of a digital PLL which uses a high-resolution time-to-digital converter (TDC) for wide loop bandwidth. The TDC uses a time amplification technique to reduce the quantization noise down to less than 1 ps root mean square (RMS). Additionally TDC input commutation reduces low-frequency spurs due to inaccurate TDC scaling factor in a counter-assisted digital PLL. The loop...
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