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The recent advancements in the implementation technologies have brought to the front a wide spectrum of new defect types and reliability phenomena. The conventional design techniques do not cope with the integration capacity and stringent requirements of today's nanometer technology nodes. Timing-critical paths analysis is one of such tasks. It has applications in gate-level reliability analysis,...
This paper proposes a complete method of diagnostic test generation for transition faults. The method creates a diagnostic test generation model for a pair of transition faults to be distinguished from a given full-scan sequential circuit and employs an ordinary transition fault ATPG tool. The proposed model supports launch-off-capture and launch-off-shift modes which is supported by the ATPG tool...
Nanoelectromechanical (NEM) relays are a promising class of emerging devices that offer zero off-state leakage and behaves like an ideal switch. The zero leakage operation has generated lot of interest in low power logic design using these relays <citerefgrp><citeref refid="ref1"/></citerefgrp>, <citerefgrp><citeref refid="ref2"> </citeref></citerefgrp>...
In this paper we propose a scheme for enhancing the timing performance of a pre-designed synchronous sequential circuit. In the proposed scheme, a circuit is driven by two clocks. One of them is the conventional clock while the other one, having a shorter period, is applied when the circuit stabilizes well before the critical delay. We use a symbolic algorithm to analyze the timing behavior of the...
Small-delay faults may escape detection by transition fault patterns, but traditional transition fault simulator can not detect this phenomenon. A fault simulator detecting test escape of small-delay faults is presented. The sizes of the faults are less than one system clock cycle. For our method, the delay distribution in the CUT is considered, and the fault size is quantized as times of the propagation...
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