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This paper proposes a highly linear source follower (S.F) circuit aiming for the front-end buffer of data convertors. The linearity is systematically improved by maintaining an invariant voltage drop between gate and source nodes of an MOSFET placing a current regulator in series with the source follower. Simulation results using 65nm CMOS technology conceal the linearity enhancement from 0.860 to...
The paper will present new high accuracy multiplier circuits, focused on the implementation of original techniques for improving the linearity of the proposed structures. The new approach of designing high precision multipliers using multifunctional cores presents the important advantage of allowing a facile reconfiguration of the designed circuits, the multiplier core being able to implement a multitude...
The paper presents an original approach of designing analog signal processing circuits, based on the re-using of the same functional core for implementing two circuit functions: signal gain with theoretical null distortions and signal squaring. The advantages of the increased modularity and controllability and of the reduced design costs represent an immediate consequence of the double function realized...
An original voltage multiplier circuit will be presented. The circuit is implemented in 0.35 mum CMOS technology and, in order to improve its frequency response, it is based exclusively on MOS transistors working in saturation region. The utilization of a FGMOST (Floating Gate MOS Transistor) for replacing the classical MOS devices allows obtaining an important reduction of the circuit complexity...
An RF power MOSFET was proposed and manufactured in a standard 0.13 μm CMOS technology. Without adding additional masks, cost and process, the breakdown voltage can be improved by using the N-well and shallow-trench-isolation processes to form a drift n- region. The breakdown voltage was 4.3 V at gate bias of 1.2 V. The cutoff frequency and maximum oscillation frequency were 68 GHz and 87 GHz, respectively...
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