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In this paper a highly linear differential CMOS low noise amplifier (LNA) for ultra-wideband (UWB) applications is proposed. The proposed LNA uses a linearization technique to improve both input second- and third-order intercept points (IIP2 and IIP3), simultaneously. The linearity is improved by canceling the common-mode part of all intermodulation (IM) components from the output current. Analysis...
One of the important components of a receiver is the low noise amplifier (LNA). The challenges of LNA design include ability to achieve high gain, low noise figure and better linearity at low power consumption within the required frequency. In this paper, our design is based on Impulse Response (IR) Ultra-Wideband (UWB) transceiver operating at 3.1–4.6GHz. Hence the LNA designed has been optimized...
This paper presents a high linearity and low power up-conversion mixer at 5.2 GHz for wireless applications. The design based on Gilbert-cell active double-balanced mixer with integrated on-chip input active balun. Core mixer employs additional parallel capacitors and the degeneration inductors to obtain high linearity. A designed active balun which converts single-ended input to differential signals...
A 2.4GHz receiver front-end with on-chip balun implemented with 0.13um CMOS technology is presented in this paper. Based on direct-conversion architecture, the front-end comprises a two-stage LNA (low noise amplifier) with optimized on-chip transformer and quadrature passive mixer. The gm-boosting technique is employed in 1st stage of LNA to achieve low noise and low current simultaneously. In 2nd...
This paper discusses the design of a 60 GHz low noise amplifier (LNA) using a standard low power SOI CMOS process from ST Microelectronics. First, we outline the technology as well as the mm-wave design challenges. Using recent work on coplanar waveguide (CPW) modeling, we describe how it's possible to use parametric, 3D electromagnetic simulation to complete or replace analytical models of on-chip...
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