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Tip to Tip (T2T) of interconnect lines in advanced CMOS is quite important when downscaling the area of SRAM and logic standard cells. When T2T size is increasing we have less space for via placement. Additionally variability could impact the yield of the Dual Damascene (DD) structure because of via placement or alignment. As we continue to extend 193i lithography for patterning block using multi-patterning...
High-performing screen printed, fire-through Si solar cells require a uniform, about 10-μm-thick, back surface field (BSF), with a peak Al concentration of about 1018 cm-3. This entails forming an ~30-μm-thick Si-Al melt, which initiates sporadically and tends to agglomerate and ball up, thus producing a non-uniform BSF. We have developed a method to stabilize the Si-Al melt by deploying Si injection...
Background and details on an optimized control plan for metal contamination monitoring have been described. It must be emphasized that this control plan can only be defined and sustained through close interaction of R&D, Metrology, Process control and Production people.
We have demonstrated high mobility pMOSFETs on high quality epitaxial SiGe films selectively grown on Si (100) substrates. With a Si cap processed on SiGe channels, HfSiO2 high-k gate dielectrics exhibited low C-V hysteresis (<10 mV), interface trap density (7.5times1010), and gate leakage current (~10-2 A/cm2 at an EOT of 13.4 Aring), which are comparable to gate stack on Si channels. The mobility...
A surface micromachining technique is proposed which significantly reduces the undesirable pattern following effect and prevents disturbance in subsequent layers of the structure. This modified lift off method starting from a flat surface embeds the base layer of microstructure in the substrate in order to maintain initial surface profile, and thus allows fabrication of subsequent layers to start...
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry...
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