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A new technique to reduce the clock jitter effect on single-bit continuous-time delta-sigma modulators (CTDSM) is proposed. It utilizes a delay line to generate N highly correlated clock sources to reconstruct the feedback waveform. Theoretical analysis show that the jitter-induced random noise power is reduced by a factor of 1/N2. Simulation results confirming the analysis are reported.
This paper presents a bit-level parallel communication interface used for inter processor communication separated on different printed circuit boards. A high performance board-to-board communication interface is important in modern supercomputers and portable computers or gadgets with multiple screen displays. We propose a recalibrated transmitter and receiver soft IP cores to support asynchronous...
In this paper, we propose a high accuracy multi-chain time interval measurement (TIM) technique by employing the dedicated carry chain of FPGA. According to the principle of delay chain time to digital converter (TDC), the proposed method is realized by connecting the selectors inside the slices. The resolution of the delay chain method is limited by the time delay of one delay unit. To break through...
This paper presents a generalised new formula for impulse-invariant transformation which can be used to convert an nth-order Discrete-Time (DT) ΔΣ modulator to an nth-order equivalent Continuous-Time (CT) ΔΣ modulator. Impulse-invariant transformation formulas have been published in many open literature articles for s-domain to z-domain conversion and vice-versa. However, some of the published works...
For pursuing the high speed information transmission, the design and research of the high speed SerDes circuit are actively developing now. Due to the requirements for long transmission path, intensive equalization and high speed transmission circuit testing function, two high speed SerDes circuits are designed and fabricated based on 130nm SiGe BiCMOS technology. One is for the research of the equalization...
A precise timing system that consists of two delay-locked loops (DLLs) is proposed to align the sampling phases of the time-interleaved ADC (TI-ADC) with the front-end Sample and Hold (S/H) clock. DLL1 using bang-bang phase detector (PD) handles the 1 GHz system clock and DLL2 produces 32 phases to generate the non-overlapped clock in the followed 4 pipeline ADCs. A new self-calibration scheme in...
In this paper a structure for high-speed incrementing/decrementing accumulator is proposed based on even and odd unit cells. Step of accumulation can be chosen among ±2n levels where n = 0, 1, 2, 3, … through a control digital word. A 10-bit accumulator is divided into two 5-bit accumulators where each one is realized in carry-ripple adder/subtractor structure. Basic cells are highly improved in number...
This paper presents a low-power on-chip RC oscillator with compensation for temperature and supply voltage variation. This circuit is based on a conventional on-chip oscillator, with only a capacitor and a comparator to avoid mismatch. Multiple current sources flow through the same resistor to generate a reference voltage. This is complemented with the dynamic element matching technique to reduce...
This paper presents a directly triggered asynchronous successive approximation register (SAR) logic with variable delay unit. With the help of the designed logic, the CDAC can be settled directly by the comparator result that avoids long propagation delay as conventional SAR logic does. Moreover, a variable delay unit is designed which provides more settling time to the last several bits to get more...
This paper presents a locking-accelerated DPLL based on multi-output bang-bang phase detector (MOBBPD) with reused most significant bits (MSBs). The bang-bang structure has simple implementation by eliminating the sensitive time-to-digital converter (TDC), while MOBBPD allows for reduced loop locking-time due to the multi-output. To further accelerate the loop locking, a scheme of reusing the MSBs...
Atomic multicast is a group communication primitive that allows disseminating messages to multiple distributed processes with strong ordering properties. As such, atomic multicast is a widely-employed tool to build large-scale systems, in particular when data is geo-distributed and/or replicated across multiple locations. However, all the most efficient atomic multicast algorithms suffer from a convoy...
To cope with data collision problem in consensus synchronization algorithm caused by utilizing pseudo-periodic broadcast method, this paper presents a novel gossip averaging based clock synchronization protocol, which combines the a synchronism of rumor communication and the robustness of neighbor averaging. We design a randomized link-activated based relative skew estimation strategy, which realizes...
The authors would like to point out the following correction in the total power consumptions recorded in Table IV of the published article <xref ref-type="bibr" rid="ref1">[1]</xref>. The total power consumptions of the proposed design and the design <xref ref-type="bibr" rid="ref2">[2]</xref> in comparison should be corrected as shown...
A novel level-up shifter with dual supply voltage is proposed. The proposed design significantly reduces the short circuit current in conventional cross-coupled topology, improving the transient power consumption. Compared with the bootstrapping technique, the proposed circuit consumes significantly less area, making it more practical for ICs with a large number of supply voltages. The minimum power-delay...
Quantum-dot Cellular Automata (QCA) is an emerging nanotechnology to reduce size as well as power consumption of switching devices for Very Large Integrated Circuits (VLSI). Moreover QCA circuits offer an advantage of very high device density, high speed, high fan out, and lower circuit complexity. The QCA based circuits have been used for implementations of basic logic gates like AND, OR, NOT as...
In this paper, we study the global clock synchronization and ranging problem for wireless sensor networks in the presence of unknown exponential delays using the two-way message exchange mechanism. Based on the Alternating Direction Method of Multipliers (ADMM), we propose a fully-distributed synchronization and ranging algorithm which has low communication overhead and computation cost. Simulation...
Techniques using modification of power supplies to attack circuits do not require strong expertise or expensive equipment. Supply voltage glitches are then a serious threat to the security of electronic devices. In this paper, mechanisms involved during such attacks are analyzed and described. It is shown that timing properties of logic gates are very sensitive to power glitches and can be used to...
In this paper, a throughput-driven design technique is proposed, in which a suspicious timing error prediction circuit is inserted to monitor the signal transitions at some selected check points. Unlike previous works where timing errors are detected after their occurrence, the proposed method tries to use the real intermediate signal transitions for timing error prediction. The check point selection...
A method of serial links output data and clock signals setup and hold times correction presented in this paper. The proposed architecture produces corrected clock which have enough setup/hold time margins respect data signal over PVT, which is needed to avoid data errors and setup/hold violations during further operation with data. The presented correction mechanism can be used in the special input/output...
Identifying speed-limiting paths is crucial for design stepping in which problematic paths are fixed or optimized so as to reach higher clock rates. Recently, using at-speed scan test patterns to identify speed-limiting paths has been reported to be a robust and effective solution. In this paper, we propose a systematic approach to find suspect path expressions (SPE) that explain the observed failing...
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