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In this paper, we introduce and evaluate ScaleMesh, a scalable miniaturized dual-radio wireless mesh testbed based on IEEE 802.11b/g technology- ScaleMesh can emulate large-scale mesh networks within a miniaturized experimentation area by adaptively shrinking the transmission range of mesh nodes by means of variable signal attenuators. To this end, we derive a theoretical formula for approximating...
The Open Distributed Processing Reference Model (ODP-RM) provides viewpoints and abstract infrastructure guidelines that can be used for a basis for enterprise architecture, especially for an inter-enterprise architecture. The ODP-RM does not prescribe methodology for modeling itself, but provides common vocabulary and focus for description. This paper performs a brief analysis of the ODP-RM (and...
It is becoming increasingly difficult to implement effective systems for preventing network attacks, due to the combination of (1) the rising sophistication of attacks requiring more complex analysis to detect, (2) the relentless growth in the volume of network traffic that we must analyze, and, critically, (3) the failure in recent years for uniprocessor performance to sustain the exponential gains...
Numerous systems have been developed to display large collections of data for urban contexts; however, most have focused on layering of single dimensions of data and manual calculations to understand relationships within the urban environment. Furthermore, these systems often limit the user's perspectives on the data, thereby diminishing the user's spatial understanding of the viewing region. In this...
In the workflow domain, many researches have been focused on such aspects as workflow system architecture, workflow task scheduling, transactional workflow, etc. Few have been concentrated on the workflow application model, design and implementation. In this paper, we firstly discuss the problems related to the individual workflow application in current workflow management systems, then show a component-based...
This paper explores the problem of efficiently permuting data stored in VLSI chips in accordance with a predetermined set of permutations. By connecting chips with shared bus interconnections, as opposed to point-to-point interconnections, we show that the number of pins per chip can often be reduced. For example, for infinitely many n, we exhibit permutation architectures with ⌈√n⌉ pins per chip...
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