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This paper discusses on prospects for area-scaling capabilities of many kinds of SRAM margin assist solutions for VT variability issue, which are based on various efforts by not only the cell topology changes from 6 T to 8 T and 10 T but also incorporating of multiple cell terminal biasing and timing sequence controls of read and write. The various SRAM solutions are analyzed in light of an impact...
The power efficiency of source-coupled logic (SCL) topology for implementing ultra-low-power and low-activity-rate circuits is investigated. It is shown that in low-activity-rate circuits, where the subthreshold leakage consumption of conventional CMOS circuits is more pronounced, subthreshold SCL (STSCL) can be used effectively for reducing the power consumption. An STSCL-based static random-access...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
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