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Regarding optimized logic network generation, recent papers have demonstrated that non-series-parallel topologies can deliver arrangements with fewer transistors when compared to the widely used series-parallel approach. However, due to its topology particularities, this paradigm represents a challenge for physical cell design, especially concerning the transistor placement procedure. In this scenario,...
Recent works demonstrate constant optimizations in the number of transistors necessary to implement some logic functions by using non-series-parallel arrangements. However, these kind of networks can produce non-dual and non-planar structures, which cannot be fully treated by some of the classical algorithms dedicated to placement. In this paper we present two methodologies to place and route non-series-parallel...
This paper describes a design flow for the circuit-level optimization of a technology. The concurrent exploration of device characteristics and library design choices leads to a more application-optimal technology. We illustrate the design flow by: 1) analyzing the impact of buffer cell design, and 2) by optimizing a 130 nm technology for low operational power.
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