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Addition is a vital operation in all data paths. The power dissipation and speed performance remain the primary factors that identify the choice of adders. To achieve the desired energy efficiency or lower power dissipation, the selection of the particular adder topology plays a major role. The operating speed of adder or the circuit latency of adder can be minimized by the use of architectures such...
This paper addresses the segmentation problem in noisy image based on Fast Edge Integration (FEI) method in active contour model (ACM) and proposes a new statistical active contour model (SACM). Two modifications are performed in FEI method. First, in order to handle noisy images, maximum log-likelihood estimation is used to replace the minimal variance term proposed by Chan and Vese. Second, a penalising...
Sublinear signal propagation delay in VLSI circuits carries a far greater penalty in wire area than is commonly realized. Therefore, the global complexity of VLSI circuits is more layout dependent than previously thought. This effect will be truly pronounced in the emerging wafer scale integration technology. We establish lower bounds on the trade-off between sublinear signalling speed and layout...
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