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Overshoot voltages during VFTLP testing of DTSCRs are investigated. The DTSCRs in a 65 nm process turn on at approximately 500 ps. The overshoot voltages from DTSCRs are shown to cause gate oxide failures when gate oxide monitors were added in parallel to DTSCR ESD devices. Scaling trends show DTSCRs turning on at approximately 150 ps when technologies are scaled down to the 32 nm node.
Since the very beginning of the flash memory era, the market has been dominated by the floating gate technology. However, as floating gate flash continues along a very steep scaling path, more and more barriers start to appear, limiting further scaling possibilities of the technology. At the same time, other concepts are preparing to take over. This paper concentrates on the prospect of high-k materials...
Simple ring-oscillator circuit has been used to estimate the degradation in circuit performance due to negative bias temperature instability (NBTI) effect but it fails to isolate the degradation from the NBTI for PMOS and the positive bias temperature instability (PBTI) for NMOS in high-K dielectric/metal gate CMOS technology. In this paper, we propose new circuit structures which monitor the NBTI...
Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry...
An extension of the conventional static CV procedure is presented which explicitely monitors the equilibrium of MOS capacitors throughout the CV sweep. Simultaneously to the static capacitance the minority carrier generation current is deduced by analyzing the time dependent displacement charge.
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