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Through-silicon via (TSV) based 3-D ICs provide a promising solution for miniaturizing chips. However, thermal issue in 3-D ICs cannot be ignored. In this paper, we proposed a method based on 3-D transmission line matrix (3-D TLM) method to calculate heat generation in the lossy silicon substrate caused by TSV induced electrical field. Pseudo random bit sequences (PRBS) at different bit rates are...
A semi-analytic approach for the electromagnetic analysis of large numbers of Through silicon vias (TSV) is presented in this paper. The method is based on cylindrical mode expansion method. The scattering and multi reflection effects between the vertical cylindrical vias are considered by expanding the electromagnetic waves surrounding the vias by cylindrical waves. As the method fully captured the...
A semi-analytic approach for the electromagnetic analysis of large numbers of Through silicon vias (TSV) is presented in this paper. The method is based on cylindrical mode expansion method. The scattering and multi reflection effects between the vertical cylindrical vias are considered by expanding the electromagnetic waves surrounding the vias by cylindrical waves. As the method fully captured the...
In this paper, the interconnection between 16×16 photodetector ROIC and substrate for the ROIC test was developed. Three kinds of substrate methods, i.e. high-density organic substrate, silicon interposer substrate and through-silicon-via (TSV) technology, were adopted. Three corresponding technical process flows were designed, and corresponding experiments were conducted. Finally, the interconnection...
Through-Silicon-Via (TSV) processing is critical to 3D chip stacked integrated circuit (IC) technology. The understanding and management of the induced stresses in silicon due to coefficient of thermal expansion (CTE) mismatch is critical for the successful implementation of this process in circuit design and production. Most TSVs in these applications are copper (Cu) filled. Analysis of Cu-filled...
Thermo-mechanical stress of tungsten-filled (W-fill) through-silicon-via (TSV) is strongly depending on via shape, size and inter-via spacing, which places constraints on TSV design, including 2-D integrated circuit layout and 3-D structure profile. This paper summarizes these constraints and co-relations among thick (up to 1.2μm) tungsten (W) film, W-fill TSV, and surrounding silicon structures,...
Thermo-mechanical stress of tungsten-filled (W-fill) through-silicon-via (TSV) is strongly depending on via shape, size and inter-via spacing, which places constraints on TSV design, including 2-D integrated circuit layout and 3-D structure profile. This paper summarizes these constraints and co-relations among thick (up to 1.2μm) tungsten (W) film, W-fill TSV, and surrounding silicon structures,...
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