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Systematic study has been performed on carrier mobility in sub-10nm gate-all-around (GAA) Si nanowire (NW) FETs on (100) SOI. The NW height is 4 - 10nm and the minimum NW width is shrunk to 5nm. For the first time, higher hole mobility than universal mobility is experimentally observed in 9nm-wide NW and even in 5nm-wide NW, demonstrating great advantage of NW pFETs, while electron mobility degradation...
Carrier transport in advanced MOSFETs is reviewed. First, electron and hole mobility in (110) MOSFETs are compared with those in (100) MOSFETs. Stress engineering is discussed in terms of energy split and effective mass due to the stress. The optimization of multi-gate MOSFET structure is then considered. As an example of ballistic MOSFETs, the performance and stress engineering of CNT FETs with doped...
The direction dependence of hole mobility in (110) SOI pFETs has been systematically investigated for the first time utilizing a new device structure. It is newly found that the high hole mobility in Si (110)/<110> even at high electric field originates from not only the large subband energy difference but also lighter conductivity mass than Si (110)/<100> caused by quantum confinement.
We report, for the first time, a simple and cost effective co-integration of strained p and n-FETs using tin (Sn) and mono-carbon (C) implant in Source/Drain (S/D) of p- and n-FETs, respectively, to induce beneficial strain. For the first time, a single laser anneal step was employed to substitutionally incorporate the Sn and C atoms simultaneously into lattice sites. 7 at.% substitutional Sn concentration...
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