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Channel Hot Carrier (CHC) and Negative Bias Temperature Instability (NBTI) degradation has been studied in pMOSFETs with and without channel strain. The results show larger CHC degradation and a neglegible influence of NBTI on strained pMOS devices. The degradation effects are modeled to be introduced in a circuit simulator. The simulations of a CMOS inverter, which has been chosen as example circuit,...
We present the reliabilities in compressively strained SiGe channel pMOSFETs. A Si capping layer in SiGe channel pMOSFETs improved the negative bias temperature instability (NBTI) without device performance degradation. Also, the Si capped device exhibits the better NBTI reliability than the Si channel device. Because a Si capped structure forms the double barrier layer in the interface, it is the...
A reliability study of high-k/metal gate stack transistors with a sub-nanometer equivalent oxide thickness (EOT) and engineered interfacial layer (IL) having a k value higher than that of conventional SiO2 thin film is reported. The mobility reduction in these ldquozerordquo SiOx IL devices exhibits a consistent trend of a positive charge buildup and increased interface state density associated with...
In this paper, we demonstrate TaN/fluorinated HfO2 CMOS devices, focusing on symmetry and asymmetry fluorine incorporation at top or bottom HfO2 interfaces. 16% permittivity enhancement, 65% and 91% mobility increases for electron and hole, respectively, under high electric field was achieved. Reliability of n- and p-MOSFET was improved 3 orders and 8% for GIDL and hot carrier immunity, respectively...
Polarities of plasma charging damage in n- and p-channel MOSFETs with Hf-based high-k gate stack (HfAlOx/SiO2) were studied for two different plasma sources (Ar-and Cl-based gas mixtures), and found to depend on plasma conditions, in contrast to those with conventional SiO2. For Ar-plasma, which was confirmed to induce a larger charging damage, both n- and p-ch MOSFETs with high-k gate stacks suffer...
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