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6Å EOT Si0.45Ge0.55 pFETs with 10 year lifetime at operating conditions (VDD=1V) are demonstrated. Ultra-thin EOT is achieved by interfacial layer (IL) scavenging. Negative Bias Temperature Instability (NBTI) is alleviated using a high Ge fraction, a thick SiGe quantum well (QW) and a thin Si cap. Hot Carrier Injection (HCI) and Time Dependent Dielectric Breakdown (TDDB) are shown also to not constitute...
A reliability study of high-k/metal gate stack transistors with a sub-nanometer equivalent oxide thickness (EOT) and engineered interfacial layer (IL) having a k value higher than that of conventional SiO2 thin film is reported. The mobility reduction in these ldquozerordquo SiOx IL devices exhibits a consistent trend of a positive charge buildup and increased interface state density associated with...
We report for the first time that extreme EOT scaling and low n/p VTHs can be achieved simultaneously. Underlying mechanisms that enable EOT scaling and EWF tuning are explained and the fundamental device parameters including reliability of the extremely scaled devices are discussed. Record low gate leakage, appropriately low VTHs and competitive carrier mobilities in this work demonstrate the gate...
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