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A novel variation of lateral thickness (VLT) technique is proposed to bring a uniform surface electric field of SOI lateral high voltage devices. Comparing to the conventional RESURF device, the linear thickness of drift region increases the breakdown voltage by 40% while decreasing the drift resistance by 50%. Furthermore, single- or two-step drift thickness can be adopted to reduce fabrication difficulties...
A non-classical device structure namely self-aligned quasi-silicon-on-insulator (SOI) metal-oxide semiconductor (MOS) field-effect transistor with pi-shaped semiconductor conductive layer (SA-piFET) is presented, seeking to improve the performance and upgrade the reliability of the SOI-based devices. Designed to equip with a SA single crystal silicon channel layer, plus a natural source/drain (S/D)...
Ultra Thin Body Si-On-ONO (UTB SOONO) transistors with ultra thin spacer are successfully demonstrated and evaluated. They have shown increased driving current more than 30% compared with conventional UTB SOONO transistors with thick spacer due to reduced source/drain resistance without short channel effect degradation by using thin spacer. In this paper, it is shown that thin spacer technology is...
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