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This paper presents the design of a 10 GHz divider using Extended True Single Phase Clock (E-TSPC) logic on a 0.18 ??m CMOS technology with 1.8 V supply voltage. This divider contains D-Flip flop with dynamic structure that is based on the ??2 divider and ??8/9 dual modulus prescaler. By optimizing the transistor size in each divider stage and inserting optimized buffers between the stages, the power...
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