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Chip-multiprocessors need low cost and high performance communication structure. Network-on-Chip (NOC) is a promising candidate because of its high scalability. In this paper, a hybrid circuit-switched (HCS) NOC is proposed. The HCS NOC uses bufferless switch and pipeline channel to construct the on-chip network. A network interface is also designed to make the HCS NOC AMBA-compatible. Packet setup...
Mitigation of radiation effects is one of the major problems for space-borne computing platforms. The presented work proposes an approach for building reliable, hardware fault adaptive stream processing platforms for space applications. The proposed concept is based on architecture-to-fault adaptation by run-time hardware reconfiguration. The concept assumes representation of system components in...
On chip many-core systems, evolving from prior multi-pro cessor systems, are considered as a promising solution to the performance scalability and power consumption problems. The long communication distance between the traditional multi-processors makes directory-based cache coherence protocols better solutions compared to bus-based snooping protocols even with the overheads from indirections. However,...
We propose a multi-voltage (multi-Vdd) variable pipeline router to reduce the power consumption of Network-on-Chips (NoCs) designed for chip multi-processors (CMPs). Our multi-Vdd variable pipeline router adjusts its pipeline depth (i.e., communication latency) and supply voltage level in response to the applied workload. Unlike dynamic voltage and frequency scaling (DVFS) routers, the operating frequency...
Power management in system-on-chip (SoC) has become one of the most crucial techniques for mobile devices. Among many intellectual properties (IPs) of SoC, a microprocessor, which is one of the major power consumers in the system, is a key component in SoC power management. Controlling idle states for microprocessors, which is typically implemented by combinations of clock gating and power gating,...
In ultra-deep submicron technology, minimizing the propagation delay and power consumption on buses is two of the most important design objectives in system-on-chip (SOC) design. Crosstalk between adjacent wires on the bus may create a significant portion of propagation delay. Elimination or minimization of such faults is crucial to the performance and reliability of SOC designs. In this paper, we...
This paper addresses the communication modelling and synthesis problem for applications implemented on networks-on-chip. Due to the communication complexity of such systems it is difficult to estimate the communication delay. On the other hand, guaranteeing the timing constraints without detailed know-how about the communication is impossible. In this work we propose a communication modelling and...
Processor allocation in todays many core MPSoCs is a challenging task, especially since the order and requirements of incoming applications are unknown during design stage. To improve network performance, balance the workload across processing cores, or mitigate the effect of hot processing elements in thermal management methodologies, task migration is a method which has attracted much attention...
Today, power management is a key design objective in chip fabrication. In this paper, we present a novel approach to reduce power consumption in SIMD based multi-core architectures. Voltage scaling technique is used, by implementing voltage islands, to optimize power and performance tradeoff for the cores. The number of islands and their respective voltage are selected based on the power-delay characteristics...
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for chip multiprocessors (CMPs). However, it is inevitable to suffer from high communication latency due to the increasing number of hops. In this paper, we attempt to accelerate network communication by exploiting communication...
With the number of processor cores increasing in chip multi-processors (CMPs) and global wire delays increasing, networks on chip have been gaining wide acceptance for on-chip inter-core communication. This paper introduces a low latency Dynamic Virtual Output Queues Router (DVOQR), which can reduce the router latency to two cycles by leveraging look-ahead routing computation and virtual output address...
This paper presents a router structure for Network-on-Chips called Quad Router which benefits from communication locality. The router can be shared among more than one Processing Element (PE), so the average hop count of a packet is decreased. This structure consists of eight input buffers and eight output ports by which two different topologies are introduced called Double-Link Mesh (DLM) and Crossbar...
This paper presents a Tabu search based approach for the topology synthesis of application-specific multicore architectures using an automated design technique. The Tabu search method incorporates multiple objectives in order to generate an optimal NoC topology which accounts for both power and performance factors. The method generates a system-level floorplan in each major stage of the topology synthesis...
Power consumption of on-chip interconnects is a primary concern for many embedded system-on-chip (SoC) applications. In this paper, we compare energy and performance characteristics of asynchronous (clockless) and synchronous network-on-chip implementations, optimized for a number of SoC designs. We adapted the COSI-2.0 framework with ORION 2.0 router and wire models for synchronous network generation...
Nowadays, the Network-on-Chip (NoC) paradigm has become more and more popular for building an on-chip communication infrastructure. Like in every traditional network, debugging and performance monitoring are also very important issues in NoC-based systems. Unfortunately, the design process of monitoring hardware is a time consuming activity. The work presented in this paper is based on a high level...
VLSI circuits of 45 nm technology and beyond are increasingly affected by process variations as well as aging effects. Overcoming the variations inevitably requires additional power expense which in turn aggravates the power and heat problem. Adaptive supply voltage (ASV) is an arguably power-efficient approach for variation resilience since it attempts to allocate power resources only to where the...
Technology scaling has led to the integration of many cores into a single chip. As a result, on-chip interconnection networks start to play a more and more important role in determining the performance and power of the entire chip. Packet-switched network-on-chip (NoC) has provided a scalable solution to the communications for tiled multi-core processors. However the virtual-channel (VC) buffers in...
In a conventional SoC designs, on-chip memories occupy more than the 50% of the total die area. 3D technology enables the distribution of logic and memories on separate stacked dies (tiers). This allows redesigning the memory tier as a configurable product to be used in multiple system designs. Previously proposed dynamic re-configurable solutions demonstrate strong dependence between read latency...
On-chip interconnection network is a crucial design component in high-performance System-on-Chips (SoCs). Many of previous works have focused on the automation of its topology design, since the topology largely determines its overall performance. For this purpose, they mostly require a switch library which includes all possible switch configurations (e.g. the number of in/output ports and data width)...
Power dissipation has been pointed out as the main limiting factor for the scaling of future CMOS circuits. Due to technology scaling, a large number of repeaters are being used in on-chip communication networks and they contribute a significant portion of the total chip power. Therefore, in this work we have characterized the leakage, short circuit and switching power dissipation for the repeaters...
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