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Intentional skew is known to be useful for improving clock frequency and/or tolerance to delay variations. This paper proposes a complete framework for treating skew schedule in the high level datapath synthesis. Major contributions include (1) the incorporation of timing issue on multiplexer-control into the skew scheduling problem (previously, only timing issue on register-control has been discussed,...
With the move to deep submicron processes, the design-productivity gap has continued to widen for RTL-based design methodologies. High-level synthesis has been touted as a solution to the design-productivity gap by allowing designers to move up to a higher level of abstraction where they focus on the functionality of the circuit instead of the low level details. However, at the same time, the move...
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