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A low-power CMOS bandgap voltage reference is designed. This bandgap voltage reference adopted advanced startup circuit and sub-threshold technology. The circuit is simulated under SMIC 0.18μm CMOS process and 1.8V supply voltage. The simulation results show that it has significantly low power and low sensitivity to the temperature. The power is only 46.468μW, and the temperature coefficient is 16...
This paper illustrates the rail-to-rail capability of a single-pair bulk-driven CMOS input stage operated from an extremely low supply voltage. A composite input stage is also introduced for performance comparison, based on experimental data obtained in standard 0.35 mum CMOS technology with a supply voltage of 1 V. Measurements demonstrate the rail-to-rail suitability of the single-pair input stage...
Channel hot-carrier (CHC) degradation in short channel transistors with a high-k/metal gate stack processed in CMOS technology has been analysed. For short channel transistors (L<0.15 mum), the most damaging stress condition has been found to be VG=VD instead of the "classical" VG=VD/2 determined for long channel transistors. In this work, we have demonstrated that this shift is not caused...
Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure. Polymorphic gates whose logic function can be controlled by the level of the power supply voltage (Vdd) represent a special class of polymorphic gates. A new polymorphic NAND/NOR gate controlled by Vdd is presented. This gate was fabricated and utilized...
The soft-error vulnerability of flip-flops has become an important factor in IC reliability in sub-100-nm CMOS technologies. In the present work the soft-error rate (SER) of a 65-nm flip-flop has been investigated with the use of alpha-accelerated testing. Simulations have been applied to study the flip-flop SER sensitivity in detail. Furthermore, an easy-to-use approach is presented to make an accurate...
There have been many solutions to create a soft error immune SRAM cell. These solutions can be broken down into three categories: a) hardening, b) recovery, c) protection. Hardening techniques insert circuitry in an SRAM cell possibly duplicating the number of transistors. Recovery techniques insert current monitors in SRAMs to detect SEUs and they employ error correcting codes or redundancy to mitigate...
The paper presents a detailed study on the idle leakage reduction techniques on partially depleted silicon-on-insulator (PD-SOI) CMOS SRAM. The most promising leakage reduction techniques that have been proposed are introduced, analyzed and compared into 65 nm low-power PD-SOI technology, taking into account all the SOI specific effect. Especially, it is shown that the leakage reduction techniques...
A non-classical device structure namely self-aligned quasi-silicon-on-insulator (SOI) metal-oxide semiconductor (MOS) field-effect transistor with pi-shaped semiconductor conductive layer (SA-piFET) is presented, seeking to improve the performance and upgrade the reliability of the SOI-based devices. Designed to equip with a SA single crystal silicon channel layer, plus a natural source/drain (S/D)...
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
Transconductance (gm) enhancement in n-type and p-type nanowire field-effect-transistors (nwFETs) is demonstrated by introducing controlled tensile strain into channel regions by pattern dependant oxidation (PADOX). Values of gm are enhanced relative to control devices by a factor of 1.5 in p-nwFETs and 3.0 in n-nwFETs. Strain distributions calculated by a three-dimensional molecular dynamics simulation...
Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry...
This paper presents a parameterized current sensor able to detect transient ionization in the silicon substrate. Each sensor is controlled by a set of trimming bits that can be used to attune the sensitivity of the sensor while compensate process and temperature variations. Electrical simulation results show that the use of this parameterized sensor can increase the number of transistors monitored...
A scaling analysis of fundamental ESD components (low voltage transistors, N-well diodes, interconnects and thin dielectrics) for the last three CMOS technology nodes (130 nm, 90 nm and 65 nm) targeting the same low-power applications is presented. The impact of technology scaling on the ESD design window will be discussed.
Substrate amorphization prior to Source/Drain implantation is used for shallow junction fabrication. The impact of preamorphization on CMOS Performance is investigated. Results for a 1.5??m double well CMOS Technology with phosphorus and boron drains are presented. The influence of preamorphization on the transistor characteristics, speed and latch-up hardness is discussed.
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