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Rapid scaling of transistor gate sizes has significantly increased the density of on-chip integrations and paved the way for many-core systems-on-chip with highly improved performances. The design of the interconnection network of these complex systems is a critical one and the network-on-chip is now the accepted efficient interconnect for such large core arrays. An unfortunate adverse effect of technology...
This paper presents a focus on the error propagation aspect which exists in interconnected networks. For handling the issues and considerations implied by this negative property, a method for ensuring fault tolerance and reliability of real-time routing processes is developed, specifying how this phenomenon's effects can be prevented. Real-time transmissions need a constant flow and require priority...
This paper presents performance and reliability evaluation of deterministic and adaptive fault-tolerant routing algorithms used in Network-on-Chip (NoC) designs. The investigated methods have a multi-level fault-tolerance capability and therefore can be separately evaluated. To illustrate the effectiveness of these methods, we conduct appropriate simulations on different applications for performance...
In recent decades, researchers try to construct high performance interconnection networks with emphasis on fault tolerance. Their studies are based on this fact that, a network can be a major performance bottleneck in parallel processors. This paper proposes an analytical model to predict message latency in wormhole-switched mesh as an instance of a fault tolerant routing. The mesh topology has desirable...
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
Networks on chips (NoCs) provide a mechanism for handling complex communications in the next generation of integrated circuits. At the same time, lower yield in nano-technology, makes self repair communication channels a necessity in design of digital systems. This paper proposes a reliable NoC architecture based on specific application mapped onto an NoC. This architecture is capable of recovering...
In this paper we present a low cost fault-tolerant attitude determination system to a scientific satellite using COTS devices. We related our experience in developing the attitude determination system, where we combine proven fault tolerance techniques to protect the whole system composed only by COTS from the effects produced by transient faults. We detailed the failure cases and the detection, reconfiguration...
This paper presents a distributed fermat-point range estimation strategy, which is important in the moving sensor localization applications. The fermat-point is defined as a point which minimizes the sum of distances from three sensors inside a triangle. This point is indeed at the trianglepsilas center of gravity. We solve the problems of large errors and poor performance in the bounding box algorithm...
Sink mobility has become an increasingly important requirement of various sensor network applications. Handling such mobile sink conditions brings new challenges to large-scale sensor networking. This investigation proposed a hybrid-structure routing protocol (HSRP) that combines the benefits of grid-based and cluster-based structures. Grid-based structure is designed to solve the cluster head selection...
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