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Helix is a recently-proposed scheme that performs IP lookup in a single memory access. Helix uses parallel prefix matching at the different prefix lengths and the position of prefixes in a binary tree for reducing the amount of memory used. The scheme enables fast table updates as prefixes are kept in their original form. In Helix, a large number of prefixes is stored in a very small amount of memory...
IP lookup plays a significant role in networking. The rapid development of the Internet brings new challenges to IP lookup in recent years. To deal with these challenges, we propose the first algorithm that we are aware of to use Minimal Perfect Hash (MPH) filters in IP lookup. It achieves the information theoretic optimum on-chip memory storage and O(1) worst case on-chip lookup speed. To overcome...
The routing and packet forwarding function is at the core of the IP network-layer protocols. The throughput of a router is constrained by the speed at which the routing table lookup can be performed. Hash-based lookup has been a research focus in this area due to its O(1) average lookup time, as compared to other approachs such as trie-based lookup which tends to make more memory accesses. With a...
In the FPGA design flow, placement remains one of the most time-consuming stages, and is also crucial in terms of quality of result. HPWL and Star+ are widely used as cost metrics in FPGA placement for estimating the total wire-length of a candidate placement prior to routing. However, both wire-length models are expensive to compute requiring O(nm) time, where n is the number of nets and m is the...
Simplicity is the major advantage of implementing hardware IP lookup engine using multi-level index tables. However, the memory efficiency of the conventional multi-level indexing approach is relatively low. In this paper we shall show that by restructuring the binary-trie using a method called bit-shuffling, highly efficient index tables to support the IP lookup operation can be built. The proposed...
In order to satisfy the performance improvement of computing speed, many researchers have been studying in areas of both processor and memory system architectures. In the area of memory system, the linear skewing scheme has been known as a suitable one for the single instrution multiple data stream (SIMD) architecture. The scheme maps the data element located at coordinates (i, j) in an M ×N data...
We propose a dual TCAM architecture - DUOS, for routing tables. Four memory management schemes for TCAMs also are proposed and evaluated. DUOS and our memory management schemes support control-plane incremental updates without delaying data-plane lookups. Compared to other TCAM architectures such as CAO OPT [19] that support incremental updates without delaying lookups, DUOS offers reduction in power...
IP address lookup is a fundamental operation in packet forwarding. Using multi-level index tables to find out the next-hop value is an attractive approach due to its simplicity. However, memory efficiency is relatively low because prefixes are sparsely distributed in the address space. In this poster, we shall outline a new approach to construct memory efficient index tables based on a technique called...
The speed of interconnection has grown continually in the fast developing Internet and other networks. Routing lookup has become the bottleneck of high-speed packet forwarding. Obviously, high-speed packet forwarding depends on high-speed routing lookup and update algorithms. This paper discusses Longest Prefix Match algorithm (LPM) based on the hardware structure of network processor (NP). The LPM...
Internet migration from IPv4 to IPv6 has introduced more challenge to IP address lookup problem. Nowadays, some existing address lookup algorithms work well for IPv4 addresses, however, few of them can scale well to IPv6 both in lookup and update speed. As IPv6 uses 128-bit addresses, schemes whose lookup time grows with address length become less attractive. In this paper, a novel level based IPv6...
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
In this paper we propose a set of different configurations of failure recovery schemes, developed for network-on-chip (NoC) based systems. These configurations exploit the fact that communication in NoCs tends to be partitioned and eventually localized. The failure recovery approach is based on checkpoint and rollback and is aimed towards fast recovery from system or application level failures. The...
We establish new upper bounds on the complexity of several "rectangle" problems. Our results include, for instance, optimal algorithms for range counting and rectangle searching in two dimensions. These involve linear space implementations of range trees and segment trees. The algorithms we give are simple and practical; they can be dynamized and taken into higher dimensions. Also of interest...
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