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This paper proposes a new dimension order routing algorithm for Mesh-of-Tree based Network-on-Chip design. It simplifies the router design as well. It results in significant saving in the energy consumed by the network. For uniform traffic, the saving is as high as 63%. It offers the flexibility of designing routers of different sizes for mapping of applications.
This paper present a new dimension-oriented routing algorithm for Mesh-of-tree (MoT) based Network-on-Chip (NoC) architecture. The addressing scheme is considerably simplified that enables us to reduce the minimum flit-size to 16-bits, compared to 32-bits in the previously reported works. The same level of throughput and average latency could be achieved with a 43.86% reduction in area and 43% reduction...
Several NoC routing schemes proposals targeting overall performance optimization are available in the literature. However, such proposals do not differentiate the application flows. The goal here is to demonstrate that adaptive routing algorithms can be used in flows with temporal constraints, enabling an enhanced degree of path exploration. The main contribution of this work is to expose the routing...
Ternary Content Addressable Memories (CAMs) are widely used in high-speed routers. They allow a longest-prefix matching operation to complete within a single clock cycle. However, TCAMs are costly and their power consumption is very high. In this paper, we identify two kinds of redundancy in the usage of TCAMs in IP route lookup, and propose a hybrid scheme which combines Binary CAMs and Ternary CAMs...
A large body of research literature has focused on improving the performance of longest prefix match IP-lookup. More recently, embedded memory based architectures have been proposed, which delivers very high lookup and update throughput. These architectures often use a pipeline of embedded memories, where each stage stores a single or set of levels of the lookup trie. A stream of lookup requests are...
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