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Software Defined Networking (SDN) is fast gaining acceptance as a networking architecture, which simplifies network management, by separating the control plane from the data plane. Edge-Core SDN is an extended SDN architecture which divides the underlying network into edge and core components. This decouples the edge switch requirements from the network core switch behaviour. When the number of networking...
A novel Denial-of-Service attack for Networks-on-Chip, namely illegal packet request attack (IPRA), has been proposed and measures to mitigate the same have been addressed. Hardware Trojans, which cause these attacks, are conditionally triggered inside the routers at the buffer sites associated with local core, when the core is idle. These attacks contribute to the degradation of network performance...
ISPs face difficulties in optimizing interdomain routing due to the single path routing constraint of BGP. A single best path makes it difficult to optimize routing and is unable to satisfy various application requirements of customers. In this paper, we present a new routing architecture for ISP edge network which breaks this constraint and allows the operator to flexibly assign interdomain paths...
Multi-core, Mixed Criticality Embedded (MCE) real-time systems require high timing precision and predictability to guarantee there will be no interference between tasks. These guarantees are necessary in application areas such as avionics and automotive, where task interference or missed deadlines could be catastrophic, and safety requirements are strict. In modern multi-core systems, the interconnect...
As integrated circuits are limited by hardware resources, reducing cost while maintaining the performance becomes especially important. In this article, we propose a conflict-free NoC (cfNoC) for the GPGPU request network. The cfNoC eliminates (i) conflicts among different columns by deploying an exclusive subnet for each column, and (ii) conflicts inside the same column by using a token-based mechanism...
Current processor design with ever more cores may ensure that theoretical compute performance still follows past increases (resting from Moore's law), but they also increasingly present a challenge to hardware and software alike. As the core count increases, the network-on-chip(NoC) topology has changed from buses over rings and fully connected meshes to 2D meshes. The question is which programming...
With the development of computer network, traditional general CPU and ASIC cannot meet the corresponding needs due to their disadvantages, nevertheless, the Network Processor(NP) finds its wide application in today's network devices because of its great balance between performance and flexibility. This paper focuses on the issues of system design and implementation of NPs. The early design method...
Probability-based approaches for phylogenetic inference, like Maximum Likelihood (ML) and Bayesian Inference, provide the most accurate estimate of evolutionary relationships among species. But they come at a high algorithmic and computational cost. Network-on-chip (NoC), being an emerging paradigm, has not been explored yet to achieve fine-grained parallelism for these applications. In this paper,...
As a promising communication infrastructure of future large scale SoC, NoC is inherently suitable to the dynamic reconfiguration technology. The combination of NoC and DR will lead a new era of computing platform. This paper presents a survey of DRNoC, discusses the current approaches and open issues organized by three aspects: the hardware architecture, the routing protocol, and the reconfiguration...
Network-on-Chip (NoC) architectures provide a good way of realizing efficient interconnections and largely alleviate the limitations of bus-based solutions. NoC has emerged as a solution to problems exhibited by the shared bus communication approach in System-On-Chip (SoC) implementations including lack of scalability, clock skew, lack of support for concurrent communication and power consumption...
Network-on-Chip (NoC) is an important communication infrastructure for System-on-Chips (SoCs). Designing high performance NoCs with minimized area overhead is becoming a major technical challenge. In this paper, we propose the on-the-fly virtual channel (VC) allocation for low cost high performance on-chip routers. By performing the VC allocation based on the result of switch allocation, the dependency...
The communication latency of Network-on-Chip (NoC) is one of the factors that significantly impacts on the application performance on System-on-Chips. To reduce the NoC latency, we propose a low latency architecture of router, which utilizes virtual output queuing (VOQ) to shorten the processing time of a packet transfer. Based on taking advantage of VOQ in buffering, the number of pipeline stages...
This paper introduces the Quarc NoC, a novel NoC architecture inspired by the Spidergon NoC. The Quarc scheme significantly outperforms the Spidergon NoC through balancing the traffic which is the result of the modifications applied to the topology and the routing elements.The proposed architecture is highly efficient in performing collective communication operations including broadcast and multicast...
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