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A novel 1.575 GHz CMOS common-mode replica compensated LC voltage-controlled oscillator with enhanced power supply rejection (PSR) is introduced for global position system (GPS) system-on chip application. In order to improve the PSR and reduce the power consumption, additional regulating circuit with feed forward and feedback amplifiers are implemented using transconductance stages with common-mode...
This paper reports a multi-channel neural recording system-on-chip (SoC) with digital data compression and wireless telemetry. The circuit consists of a 16 amplifiers, an analog time division multiplexer, an 8-bit SAR AD converter, a digital signal processor (DSP) and a wireless narrowband 400-MHz binary FSK transmitter. Even though only 16 amplifiers are present in our current die version, the whole...
This paper examines the design of full feed-forward sigma-delta modulator which is much more suitable for the CMOS digital process with low supply voltage than the traditional second-order feedback loop. The full feed-forward system reduces the modulator's sensitivity of the circuit nonidealities and decreases the internal signal swing to half the full scale. An implementation in a 0.35 ??m CMOS technology...
In this paper a 12 bits 50 kS/s micropower hybrid ADC is proposed for biomimetic microelectronic systems using 0.18 mum CMOS process. The hybrid ADC combines SAR and dual-slope architectures to achieve 12 bits, power consumption 60 muW, and small silicon die size. This hybrid ADC shows very good figure-of-merits (FOM) on both power consumption and silicon die size compared with conventional low power...
An ASK demodulator with a high bandwidth for lower ISM band frequencies is presented. A total of 15 MOS transistors are used in the proposed design without using any passive element. It is very compact to be integrated in an SOC (system-on-chip) for wireless communication biomedical applications, particularly in biomedical implant. The proposed design with a low area cost and low power consumption...
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