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Current mode (CM) scheme provides suitable alternative for the high speed on-chip interconnect signaling. This paper presents a energy-delay optimization methodology for the current-mode (CM) signaling scheme. Optimization for the CM circuits for on-chip interconnects requires a joint optimization of driver and receiver device sizes, as their parameters which affect the energy-delay performance depend...
This paper describes a design flow for the circuit-level optimization of a technology. The concurrent exploration of device characteristics and library design choices leads to a more application-optimal technology. We illustrate the design flow by: 1) analyzing the impact of buffer cell design, and 2) by optimizing a 130 nm technology for low operational power.
A variable fractional delay (VFD) filter is presented that constitutes an efficient alternative to the usual Farrow structure. The filter is constructed by multiplying the signal to interpolate by a window with proper truncation properties, and then applying the sampling theorem. The resulting interpolator involves less arithmetic operations than the existing variants of the Farrow structure. Besides,...
In this paper, we introduce a pricing model that ensures efficient resource allocation that provides guaranteed quality of service while maximizing profit in multiservice networks. Specifically, a dynamic allocation policy is examined that relies on online measurements while each service class operates under a probabilistic bound delay constraint. We present a rigorous analysis of the properties of...
In this paper, we propose a cross-layer optimization approach that exploits retransmission diversity in wireless CDMA communications. Conventionally, data packets that are not correctly detected are usually dropped. These dropped packets can be used to help data packet detection. By exploiting all the retransmitted packets, data packets can be correctly detected with higher probability. The proposed...
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