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Stochastic computing using simple logic circuits requires significantly less area and consumes less power compared to traditional computing systems. These circuits are also inherently fault-tolerant. The main drawbacks of these systems include long latency and inexactness in computing. The deviation from exact values increases as the correlation among inputs increases. In many applications, outputs...
In this paper, we present a novel statistical full-chip leakage power analysis method. The new method can provide a general framework to derive the full-chip leakage current or power in a closed form in terms of the variational parameters, such as the channel length, the gate oxide thickness, etc. It can accommodate various spatial correlations. The new method employs the orthogonal polynomials to...
This paper proposes a new approach to analyze crosstalk of coupled interconnects in the presence of process variations. The suggested method translates correlated process variations into orthogonal random variables by principle component analysis (PCA). combined with polynomial chaos expression (PCE), the technique utilizes Stochastic Collocation Method (SCM) to analyze the system response of coupled...
We present a generic method for analyzing the effect of process variability in nanoscale circuits. The proposed framework uses kernel and a generic tail probability estimator to eliminate the need for a-priori density choice for the nature of circuit variation. This allows capturing the true nature of the circuit variation from a few random samples of its observed responses. The data-driven, non-parametric,...
The dramatic increase in leakage current, coupled with the swell in process variability in nano-scaled CMOS technologies, has become a major issue for future IC design. Moreover, due to the spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for logic gates leakage under statistical...
In this paper, we propose a robust STBC transmission scheme to combat the timing synchronization errors over frequency-selective multiple-access channels. First, the equivalent channel model in the presence of timing synchronization errors is derived and we find that the synchronization errors result in an equivalent channel model with larger number of correlated channel taps. Based on this correlated...
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