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This paper presents an efficient design-space exploration method to identify the Pareto solution for the relation between the execution time and the hardware area. Initially, our method takes a particular system mapping that is surely in the Pareto solution, and then repeats the local search and the update of the Pareto solution until the Pareto solution reaches a steady state. Compared to genetic-algorithm-based...
In this paper, we present a novel technique for online testing of feedback bridging faults in the interconnects of the cluster based FPGA. The detection circuit will be implemented using BISTER configuration. We have configured the Block Under Test (BUT) with a pseudo-delay independent asynchronous element. Since we have exploited the concept of asynchronous element known as Muller-C element in order...
An adaptive LZW algorithm for compressing partial bitstreams of Virtex FPGAs was presented. The adaptations of algorithm were based on analysis of the three-level data regularity of the configuration bitstreams. Partial bitstreams were created through Xilinx module-based partial reconfiguration flow. The experiment demonstrated down to 43.69% compression ratio for partial bitstreams of several real-world...
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