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This work describes a pipelined architecture targeting FPGA binary field multiplication. It comprises a generic real time crypto coprocessor able to operate over any field, without a specific vendor specific technology. A performance comparison of this synthesized coprocessor is presented for two major FPGA vendors. The results show that the parallelism levels, often applied as a key point for decision-making,...
Since the invention of microprocessors around 1970, CPU performance improvement together with the Instruction Level Parallelism (ILP) had been the main focus of the computer industry. Recently, ILP seemed to have reached its limit and together with the problem of power consumption and heat dissipation, emerged the multi-core era. The focus had shifted from ILP to Thread Level Parallelism (TLP) and...
Thanks to the improvements in semiconductor technologies, extreme-scale systems such as teradevices (i.e., composed by 1000 billion of transistors) will enable systems with 1000+ general purpose cores per chip, probably by 2020. Three major challenges have been identified: programmability, manageable architecture design, and reliability. TERAFLUX is a Future and Emerging Technology (FET) large-scale...
The DySER (Dynamically Specializing Execution Resources) architecture supports both functionality specialization and parallelism specialization. By dynamically specializing frequently executing regions and applying parallelism mechanisms, DySER provides efficient functionality and parallelism specialization. It outperforms an out-of-order CPU, Streaming SIMD Extensions (SSE) acceleration, and GPU...
In image and video coding field, an effective compression algorithm should remove not only the spatial, temporal, and statistical redundancy but also the perceptual redundancy information from the pictures. Many perceptual models are presented in the literature to cooperate with video coding system to obtain significant bit rate reduction without perceptual distortion. One of the critical issues for...
Embedded processors are expected to immigrate towards self-reconfigurable architectures, and in the near future, the self-reconfiguration concept will be able to support revolutionary architectural innovations. The research described in this paper is a continuation of our previous work [1]. In [1], the advantage of the - so called - pessimistic run-time profiling approach was demonstrated and compared...
Most of scientists except computer scientists do not want to make efforts for performance tuning with rewriting their MPI applications. In addition, the number of processing elements which can be used by them is increasing year by year. On large-scale parallel systems, the number of accumulated messages on a message buffer tends to increase in some of their applications. Since searching message queue...
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