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This paper reports the development of electrically conductive, polymer nanofibers fabricated by electrospinning and electroless copper plating. The electrospun nanofibers were made using a precursor consisting of styrene-isoprene-styrene (SIS) block copolymer and silver trifluoroacetate. For process development and materials characterization, the fibers were electrospun as a thin membrane on glass...
Semiconductor packages with 23 um copper bond wires are decapsulated by an atmospheric pressure Microwave Induced Plasma (MIP). Potential damage to the copper bond wires due to fluorine or oxygen radicals in the plasma is investigated. Parameters like CF4 amount, input power level, and O2 addition that may influence the Si3N4 passivation etching rate are evaluated. Theory behind the changes in Si...
Slow-wave sheet beam amplifiers are under development at NRL to demonstrate 50 watts CW at 220 GHz. We report on the microfabrication of amplifier gratings based on Ultraviolet Lithography (UV-LIGA) techniques using the SU-8 Photoresist for thick films. Deep Reactive Ion etching (DRIE) has also been investigated for grating circuits. An improved cold test fixture is being developed for the cold test...
To meet future 3D stacking requirements on wafer-to-wafer level, we successfully demonstrate oxide-oxide direct bonding on 200 mm with and without copper level utilizing face-to-face alignment and bonding within one process module as well as on the same chuck.
We report a process development route towards 300 mm production-worthy non-Bosch through-silicon-via (TSV) etch with critical dimensions and via spacing between 1-5 mum and aspect ratios (ARs) up to 20:1 for 3D logic integration. This was performed on an experimental alpha-tool from Tokyo Electron: a magnetically enhanced capacitively coupled plasma etcher with a dipole ring magnet upgrade that aims...
We aim to fill the processing gap in 300 mm wafer-scale non-Bosch TSV etch process by developing production-worthy TSV etch solutions for logic-centric 3D integration. This is based on a magnetically-enhanced capacitively-coupled plasma (CCP) etching system. Key factors in this system that contribute to the control of via features such as global sidewall tapering, local sidewall roughness, Si etch...
A neutron activation system is under development to measure neutron fluence on the first wall and to evaluate total fusion power from ITER plasma. This system utilizes the method of counting gamma radiation from the metal sample irradiated by the neutron flux at the irradiation end near the plasma. Evaluation of the operational activity of the sample, which has been induced during ITER operation,...
Crystalline silicon photovoltaic (PV) industry is growing at an average rate of ~ 15%. Continuing carbon-based fuel depletion in combination with increasing green house effects will continue to add to this robust growth trend. Conservative estimates indicate that PV market will reach ~ 100 GWp/year before the year 2020. In order to sustain such production levels, impact on materials and supplies supporting...
We have been developing a novel Wafer Level Packaging technology which has a possibility of lowering WLP cost drastically by applying some Jisso techniques to WLP manufacturing processes. In short, our idea is laminating a Cu wafer having Cu bumps to a Si wafer in which LSIs are formed with a nonconductive thermosetting resin. The process flow of the developed WLP technology is as follows; 1. Cu bump...
This paper presents a study on the contact resistance of interconnects between chip and package of embedded chip technology. Multi-layered aluminum/titanium tungsten/copper interconnects (Al/TiW/Cu) were used as the model system. Design of experiment was carried out to characterize the effect of under bump metallurgy deposition steps, including the degas and radio frequency (RF) plasma etch steps,...
In this study, bottom-up electroplating is used for TSV (Through Silicon via) fabrication. With the metal temporarily bonding technology, we could remove the handling substrate and perform the chip stacking process. The TSVs made by bottom-up electroplating do not need the expensive MOCVD seed layer deposition and special designed electroplater/solution. Moreover, it is independent with the DRIE angle...
An independent-gate four-terminal FinFET SRAM have been successfully fabricated for drastic leakage current reduction. The new SRAM is consisted of a four-terminal (4T-) FinFET which has a flexible Vth controllability. The 4T-FinFET with a TiN metal gate is fabricated by a newly developed gate separation etching process. By appropriately controlling the Vth of the 4T-FinFET, we have successfully demonstrated...
ldquoDevelopment for advanced thermoelectric conversion systemsrdquo supported by the new energy and industrial technology development organization (NEDO) has been successfully completed as one of the Japanese national energy conservation projects. Three types of the cascaded thermoelectric modules operating up to 850 K in high electrode temperature and two types of Bi-Te thermoelectric modules operating...
The polycrystalline samples of BaSi2, SrSi2, and LaSi were prepared by spark plasma sintering (SPS). The electrical resistivity (rho) and Seebeck coefficient (S) were measured above room temperature. The S of BaSi2 was negative and the absolute values were rather high (-669 muVK-1 at 337 K). The S of SrSi2 was positive and the absolute values were lower (118 muVK-1 at 332 K) than those of BaSi2. For...
Nanostructuring is one of the effective approaches to lower the thermal conductivity of materials. Nanostructured skutterudite-related compounds CoSb3, Fe0.5Ni0.5Sb3, Fe0.25Ni0.25Co0.5Sb3 and Te-doped CoSb3 were synthesized by a solvothermal route. The bulk materials were prepared by hot pressing or spark plasma sintering from the solvothermally synthesized nanopowders. The thermal conductivity values...
A series of seven XRD and four p-i-n detectors with K- and L-filters was employed to measure absolute time resolved spectra of 200-ns 200-kA molybdenum and copper X-pinch plasmas.
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