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In this paper, patterned Cu and Si substrates are interconnected via solder alloys through Al/Ni self-propagating nano-film to obtain hermetical packaging for infrared detector. During the joining process, substrates which are coated with different solder layers (e.g. Sn and AuSn) are bonded under various atmospheres. By optimizing joining parameters, reliable metallurgical joints between Si/Cu and...
Recently, three dimensional integration circuits technology has received much attention because of the demands of gradually increasing functionality and performance in microelectronic packaging for different types of electronic devices. For 3D chip stacking, high density interconnections are required in high-performance electronic products. Though the bumping process used could be either electroplating...
Silicon die stacking with low-volume interconnections is an attractive method for 3D integration. It offers such benefits as extension to fine-pitch integration, increased vertical heat transfer and hierarchy for repeated thermal processes without re-melting. The process uses low-volume solder to form joints of few microns high. The low-volume solder mostly forms intermetallic compounds with underlying...
In this study, silicon (Si) chips were bonded to 304 stainless steel (SS) substrates using silver-indium (Ag-In) binary system without any use of flux. 304SS substrates were also bonded to 304SS substrates to develop low temperature fluxless processes to bond and seal two 304SS parts together. In the bonding design, Ag and In were deposited separately in layered structure. Various processes and solutions...
We performed stacking experiments on Si dies using annular tungsten TSVs (Through Silicon Vias) and Cu studs with low-volume solder micro-bumps. Unlike standard 100-micron C4 (Controlled Collapse Chip Connection) solder balls, very small solder volumes (< 6 microns in height) form IMC (InterMetallic Compounds) in the junctions during the bonding or reflow processes. The two interconnect metallurgies...
For the demand of multi-function and higher performance in electronic devices, the three-dimensional chip stacking technology with fine pitch and high input/output (I/O) interconnections has emerged recently. In addition, with the joint size becoming smaller, the current that each solder bump carried continues to increase, resulting in high current flowing in each individual joint. Therefore, electromigration...
Electroless Ni-P plating is cost effective process to fabricate UBM for solder flip chip. Thickness of electroless Ni-P UBM is important factor for mechanical and electromigration reliability. Pb-free solder flip chips with different UBM thicknesses of 3, 5 and 10 mum were prepared. First, the effect of UBM thickness on mechanical reliability was investigated. Before underfilling, flip chips using...
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